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Simulation and plot of switch on-resistance (Read 7621 times)

JJ New Member Offline Posts: 3	Simulation and plot of switch on-resistance Jan 16^th, 2005, 12:31pm Hello folks. Very nice to find such a great forum. I am using Cadence to design a switched-capacitor circuit. I am wondering how to simulate the CMOS switch on-resistance and plot it against Vgs -Vth for fixed devices size. Could anyone show me the way? Thanks a lot in advance.
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ywguo

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Posts: 943
Shanghai, PRC

Re: Simulation and plot of switch on-resistance
Reply #1 - Jan 16^th, 2005, 9:17pm

Hi, JJ,

I plot on-resistance of MOS switch using the following card in SPICE.

.probe ron=par('(v(in)-v(out))/I1(MS)')

where ron is the on-resistance of MOS swtich. v(in) and v(out) is input voltage and output voltage of that switch, respectively. MS is the MOS switch.

Make your MOS switch in normal operating mode and run a transient simulation.

Good luck

Yawei

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boa Junior Member Offline Posts: 31	Re: Simulation and plot of switch on-resistance Reply #2 - Jan 18^th, 2005, 3:58pm This thread might be helpful to you: http://www.designers-guide.com/Forum/?board=analog_design;action=display;num=107...
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