I am working on a high speed pipeline ADC. I have designed a bandgap circuit. The voltage from bandgap must be buffered to drive the reference pin of ADC such as Vrefp, Vrefn and Vcom. How can we ensure that the voltage refence buffer can settle to a desired resolution in half of clock period?  Does the buffer need large external capacitor? Could you please give me some idea reference, web resorce voltage reference buffer design in high speed design?

Hi,

you can feed the bandgap voltage in to a very slow buffer. The buffer only serves to isolate the original referance voltage generator from the switching noise. To the output of the buffer is taken off-chip,  and bypassed say by a 0.01uf in parallel with 0.1uf, they supply all the required charge.

Typically  you might have to add a series damping resistor to the capacitor to damp out any oscillations, due to the inductance inherent in the bond wire, board trace etc. Inaddition you also have to model, the inductance of the bus inside the chip that routes the reference. It is advisable to use a flipchip package with multiple bondpads allocated for reference  to minimize parasitic inductance.

There are not many references available, try

The scheme here is slightly different, does not use a buffer but just a resistor ladder with external bypass, the principle is the same.

A Highly Integrated Analog Baseband Transceiver
Featuring a 12-bit 180MSPS Pipelined A/D Converter for
Multi-Channel Wireless LAN, K. Gulati, C. Munoz, S.
Cho, G. Manganaro, M. Lugin, M. Peng, A. Pulincherry,
J. Li, A. Bugeja, A. Chandrakasan and D. Shoemaker,
Engim, Inc., Acton, MA

There is also a paper from Analog devices by Larry singer, don't quite remember which one.

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Please refer to
http://www.designers-guide.org/Forum/?board=ms_design;action=display;num=1093223...


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