Hi,
I am not sure the technology that you are using. I have seen better than 11.4 bits matching in 0.25 um cmos process, with conventional layout techniques. One way see this is to run (let us say u have a high speed 200 msps ADC) adc at say 75 msps. Now the error is dominated by cap mismatch. I have seen about 11.4 bit enob or sndr for a 13-bit resoultion adc
restict the signal flow in one direction in the array. example: input switches connected to the bottom plate, all on the lower part ofthe array. The top plate routing, all on the upper side goes to the opamp virtual gnd. That should help.
do not cross routing on top and bottom plate of the same unit cap . This will directly add parasitic to the explcit cap.
I am not sure why u are using metal1 for mim caps . usually they use higher level metals with special dielectic in between. Also make the bottom plate larger to reduce fringing fields.
Back annotate the routing both r and c into the schematic.
try
http://www-mtl.mit.edu/~daihyun/papers/designmethodology/centroidcap.pdffor more insights.