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Behaviral modelling of dc-dc voltage converters (Read 646 times)
Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #45 - Apr 11th, 2006, 6:38pm
 
The resistive current sensor trick also solves the convergence problem with the boost converter when the input inductor has series resistance.

-Eugene
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akai_densha
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Re: Behaviral modelling of dc-dc voltage converter
Reply #46 - Apr 12th, 2006, 6:08pm
 
Eugene-san

Thank you so much!
Your solution solves problem.

In my opinion, ideal current source series with voltage source caused problem.

Tanaka
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Tommy
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Re: Behaviral modelling of dc-dc voltage converter
Reply #47 - May 9th, 2006, 7:22am
 
Eugene wrote on Mar 21st, 2006, 1:23pm:
The phase should be interpreted as phase margin.


Thanks, Eugene,
But Iam not sure I understood this line
-Tom
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #48 - May 9th, 2006, 11:42pm
 
Hi Tom,

Consider a simple feedback system composed of two blocks (H and F) and an error amplifier. Let the forward gain, the gain from input to output when the feedback is disconnected, be H. Let the gain from the output to the negative input of the error amplifier by F. The closed loop transfer function, G, is

G = H/(1+FH).

The loop gain is FH. Let the phase of FH when |FH|=1 be x. Phase margin is defined as x-(-180) degrees. Note that FH does not include the sign inversion introduced by the feedback input of the error amplifier. However, when you insert a voltage source in the loop and compute the gain from one side of the source to the other, you are computing -FH because the signal propagated through the negative input of the error amplifier. Let the phase of -FH when |-FH|=1 be y. In general, the phase of -FH is the phase of FH+180. Since |-FH|=|FH|, y =x+180. Thus, y equals the phase margin of FH.

Did this answer your question?

-Eugene
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Tommy
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Re: Behaviral modelling of dc-dc voltage converter
Reply #49 - May 11th, 2006, 1:18am
 
Thanks a lot Eugene.
This forum's a lifesaver Smiley
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richard88
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Re: Behaviral modelling of dc-dc voltage converter
Reply #50 - Jun 19th, 2006, 3:36pm
 
Eugene,
 Could you post the schematics of the boost and buck example ? It would be a good confirmation for my understanding.

Thanks,
Richard


Eugene wrote on Apr 4th, 2006, 11:12am:
Here's the boost circuit I'm trying. The 10pico Ohm resistor works but 100pico Ohms causes convergence errors. Anyway, the new switch model has duty cycle clamping. The model is not yet smart enough to change conduction modes on the fly. It's possible with macro models, I have just not tried it yet with VerilogA. The basic switch model is the same. I've just reconnected it to model a boost converter instead of a buck converter.

-Eugene

Code:
// Generated for: spectre
// Generated on: Apr  4 11:03:02 2006
// Design cell name: boost
// Design view name: schematic
simulator lang=spectre
global 0
include "/tools/dfII/samples/artist/ahdlLib/quantity.spectre"

// Cell name: boost
// View name: schematic
L1 (net27 net13) inductor l=1u
C0 (net25 net052) capacitor c=20u
C2 (net25 0) capacitor c=10u
C3 (net37 net33) capacitor c=1u
R8 (net052 0) resistor r=2
R9 (net035 net27) resistor r=10p
R1 (net25 0) resistor r=10
R2 (net33 net25) resistor r=10K
R3 (0 net33) resistor r=10K
I7 (net25 0 net13 net032) DcDcX
V0 (net035 0) vsource dc=3 type=dc
V6 (net42 0) vsource dc=4.5013 type=dc
V3 (net032 net39) vsource mag=1 type=dc
E0 (net37 0 net33 net34) vcvs gain=-100
E1 (net39 0 net37 0) vcvs gain=1/2.0
V2 (net34 net42) vsource type=pulse val0=0.0 val1=100.0m period=10 \
	  delay=1p rise=1n fall=1n width=1
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=25 \
    tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
    sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=10m write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
ac ac start=.001 stop=10M dec=20 annotate=status
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub
ahdl_include "/DcDcX/veriloga/veriloga.va"
 



Code:
//Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"

module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;
electrical intrn;

real dutycycle;
analog begin
   if (V(dr)>1) dutycycle = 1;
   else if (V(dr)<0) dutycycle = 0;
   else dutycycle = V(dr);
   I(iin,gg) <+ I(intrn,vout)*dutycycle;
   V(intrn,gg) <+ V(iin,gg)*dutycycle;
end
endmodule

 


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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #51 - Jun 23rd, 2006, 11:22am
 
I've attached the buck schematic...I think.
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buck.jpg
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #52 - Jun 23rd, 2006, 11:23am
 
Here's the boost schematic.
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boost.jpg
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richard88
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Re: Behaviral modelling of dc-dc voltage converter
Reply #53 - Jul 8th, 2006, 4:04pm
 
Hi Eugene,
 Thanks for the post.
 I've further questions  ;D :
Q1:  The way you model the switch model is similar to
what written in the paper written by Edwin van Dijk et al "PWM-Switch Modeling of DC-DC Converters", 1995 IEEE Trans of Power Electronics, am I right ?
I find that it is important for the boost converter
statement : if V(dr)>1==>dr=1, elseif V(dr)<0==> dr=0,
or else the system won't work.
 
Q2:  I understand that you define the node intrn (for
buck) is for convergence purpose. I just wonder how
would the simulator knows that the node vout and intrn
are connected together ? Because what we want to see
is at the pin vout and not intrn. Is it via the
statement "I(iin,gg) <+ I(intrn,vout)*V(dr);" ?

Q3:
For boost converter, since iin is defined as inout, it
seems the current I(iin,gg) means current flowing out
of node iin from node gg, is it correct ? By the way,
how would the simulator knows that it is serving as
output ?

Q4 (most puzzling) :
I simulated the boost system with the veriloga code.
Plotting the magnitude and phase response across the
vdc (acm=1) terminals, I got the waveform as attached.
From my understanding, the complex pole of the power
train is at (1/2*pi)*(vin/sqrt(L*vout)) which gives
159Hz,
and the right hand plane zero is at
(1/2*pi)*(Rload/L)*(vin/vout)^2 which gives 177kHz,
the waveform I had shows gain peaking at 14kHz, I
wonder how it can be explain. The waveform from
simulating buck system is okay, but the boost system
can be interesting.



Thanks,
Richard
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #54 - Jul 13th, 2006, 1:29pm
 
Hi Richard,

Sorry for the delayed response. I've been really pressed for time. I have time now because I'm waiting for a simulation.

A1: I am not familiar with the Dijk paper but it is possible the switch I used is based on that one. I think I learned of the universal switch from Voperian's book. Perhaps he got it from the Dijk paper.

A2: Yes. If you don't assign a voltage across the current probe, like you might for a resistor, the voltage across the probe is zero.

A3: VerilogA defines positive current as flowing into the ii node and out of the gg node. The ii node is declared as a bidirectional probe. However, whether it sources or sinks depends on the the duty ratio and I(intrn,vout).

A4: I will have to answer this one later when I have more time to look at it. Sorry.
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #55 - Jul 17th, 2006, 1:33am
 
Hi Richard,

I finally got around to looking at your last question.  I compute the zeros of the loop gain to be at

{-3978.87, 176839.} Hz,

and the poles to be at

{-4533.75, -4497.21 - 15059.1*j, -4497.21 + 15059.1 *j} Hz

and the crossover frequency to be at

{f -> 191.568} Hz

using Mathematica. This appears to be consistent with the Spectre simulation. I guess I don't see the issue. Without the integrator, the circuit is a third order system. The complex pole pair of the third order system lies at 15KHz, which explains the peaking.


Also, please refer to my entry on 4/11. Replacing the current sensor with a resistive sensor makes the model more robust. In that case, there will be a slight voltage drop across the current probe but you can make the resistance small enough to make the voltage neglibible.

-Eugene
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sonugoyal
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Behaviral modelling of dc-dc voltage converters
Reply #56 - Apr 24th, 2008, 2:19am
 
hi all
please provede me the verilog-a model for voltage regulator and bandgap reference,
i have started to work on verilog-a one week back
i need it
please do help for me
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sheldon
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Re: Behaviral modelling of dc-dc voltage converter
Reply #57 - Apr 24th, 2008, 8:41am
 
Sonugoyal,

  What are you trying to do? Since a Bandgap reference is just a fixed voltage why not
use a voltage source? If you are using ADE, there are reference libraries with op-amp
models: ahdlLib and bmslib. These libraries also include comparator models and are
usually sufficient to get started with design. Are you looking for anything special in the
models? That is, the models have limitations if you are trying to complex functional
verification, for example, what happens when the op-amps inputs are higher than the
power supply voltage. These types of conditions can happen in multiple supply power
management designs and require more sophisticated models.

                                                                           Best Regards,

                                                                              Sheldon
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ywguo
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Re: Behaviral modelling of dc-dc voltage converters
Reply #58 - Jun 3rd, 2014, 12:02am
 
Hi Eugene,

What is the use of V2 in both buck converter and boost converter macro model? It is a pulse voltage source of 10s period, but the transient analysis stops at 10ms.

Best Regards,
Yawei
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