richard88
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Hi Eugene, Thanks for the post. I've further questions ;D : Q1: The way you model the switch model is similar to what written in the paper written by Edwin van Dijk et al "PWM-Switch Modeling of DC-DC Converters", 1995 IEEE Trans of Power Electronics, am I right ? I find that it is important for the boost converter statement : if V(dr)>1==>dr=1, elseif V(dr)<0==> dr=0, or else the system won't work. Q2: I understand that you define the node intrn (for buck) is for convergence purpose. I just wonder how would the simulator knows that the node vout and intrn are connected together ? Because what we want to see is at the pin vout and not intrn. Is it via the statement "I(iin,gg) <+ I(intrn,vout)*V(dr);" ?
Q3: For boost converter, since iin is defined as inout, it seems the current I(iin,gg) means current flowing out of node iin from node gg, is it correct ? By the way, how would the simulator knows that it is serving as output ?
Q4 (most puzzling) : I simulated the boost system with the veriloga code. Plotting the magnitude and phase response across the vdc (acm=1) terminals, I got the waveform as attached. From my understanding, the complex pole of the power train is at (1/2*pi)*(vin/sqrt(L*vout)) which gives 159Hz, and the right hand plane zero is at (1/2*pi)*(Rload/L)*(vin/vout)^2 which gives 177kHz, the waveform I had shows gain peaking at 14kHz, I wonder how it can be explain. The waveform from simulating buck system is okay, but the boost system can be interesting.
Thanks, Richard
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