Hello

Trying to run UltraSim simulation from Virtuoson Schematic Editor, I receive the following message in si.log file

Running simulation in directory: "/dir1/proj/UltraSim.run1".

Begin Incremental Netlisting Nov 15 15:01:22 2006
ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectre cmos_sch cmos.sch schematic veriloga" for instance I1 in cell TB_0.
Either add one of these views to: Library: 90131BA_DIGITAL Cell: test_case0 or modify the view list to contain an existing view.
End netlisting Nov 15 15:01:22 2006
"Netlister: There were errors, no netlist was produced."


Simulation did not complete.

Instance I1 in TB_0 cell is verilog testbench, which I imported using icms-log/File/Import feature.

Where can I find view list to add functional view?

Thanks in advance

Pavel

Thanks Bernd

What "pure"  UltraSim simulation means?
Before I run UltraSim in this manner
1. Virtuoso Schematic Editor -> Tools -> Simulation -> UltraSim
   UltraSim menu appears
2. UltraSim -> Netlist/Simulate...
Message cited in my previous message was result of these actions

Now I changed approach:
1. Virtuoso Schematic Editor -> Tools -> Analog Envirnment
2. Analog Envirnment -> Setup -> Simulator/Directory/Host...
   - Simulator/Directory/Host... -> Simulator -> UltraSim
3. Analog Envirnment -> Setup -> Environment
   Switch View List: spectre cmos_sch cmos.sch schematic functional
   Stop View List: symbol
4. Choose Analyses -> tran, Stop Time: 10m
5. Analog Envirnment -> Netlist and Run...

This provoke the following message in icms-log window:

Netlist Error: The HDL cell-view "90131BA_DIGITAL" "test_case0" "functional" does not have view-specific
           simulation data.  To create the data please open and save the view.
           You may also update the view by executing the following SKILL command:
           ahdlUpdateViewInfo("90131BA_DIGITAL" ?cell "test_case0" ?view "functional")
End netlisting Nov 15 16:47:53 2006
"Netlister: There were errors, no netlist was produced."

test_case0 is just verilog-coded testbench.

What this error means?

Regards.

Pavel

Thank you for answer Bernd

The total design is complex. Verification with Spectre will take some days.
So, I try to test it using UltraSim.
It (design) consists of 2 parts - digital (schema generated from synthesis tool) and analog (made in Virtuoso Schematic Editor).
Digital stimuli is coded in verilog (test_case0 module).
Trying to validate UltraSim simulation (it's first time I try to use it) I didn't include analog part.
So for the moment my schema consists of 2 blocks - stimuli (verilog code) and digital part (schema generated from synthesis tool).
I don't have transistor level representation of verilog block as it is just stimuli.

Change to AMS Designer means use AMS PlugIn in Hiearchy Editor?

Regards.

Pavel.

Quote:


How? In Analog Environment window I found nothing concerning AMS.

Quote:


Gates are vendor library gates. Sure,  there should be gate level netlists for them.
The vailable views are: symbol, msps, layout, extracted, cmos_sch, abstract.

Regards.

Pavel.

Quote:


Yes it does present Setup -> Simulator/Directory/Host... -> Simulator -> ams.
When I click on Ok, following message appears in icms-log window:
*Error* You must be viewing a 'config' viewType to run Artist with ams.

But I have config view for this cell..?

Quote:


Yes, its true

Quote:


If you mean Switch View List (Setup->Enviroment) I think it's due to the fact that
my stimuli block is in verilog (functional view).

Quote:


Verilog stimuli is huge, so this conversion would be combersome.

Regards.

Pavel.

Ok, now it's clear, thanks.

I just tried this approach.
1. Run config view (Hierarchy Editor (HE) + Virtuoso Schemaic Editor (VSE))
2. Run ADE from VSE.
3. In Setup -> Simulator/Directory/Host... -> Simulator choosed ams simulator
4. Specified simulation time.
5. Run simulation.

Compilation/netlisting was OK apart from many warnings like below (is it important?).
\w *WARNING* Cannot open pc.db for ("D_CELLS" "DFRS" "functional").
\w      Hierarchy below (90131BA_DIGITAL.TB_0:schematic)I0.(90131BA_DIGITAL.mlx90131_topdig:schematic)u_
core_u_atpg_top_u_oper_u_send_fsm_FSendS_reg_1.(D_CELLS.DFRS:functional) will not be expanded.

Elaboration stopped with strage error:
ncelab: *F,DLNFS: Packed library for '90131BA_simulations' was either corrupt or the file system cache consistency check failed. To correct the problem, remove the packed library, and recompile. If the problem persists, contact Cadence Design Systems.

'90131BA_simulations' is library where our Spectre simulations are stocked. It isn't corrupted as we use it with Spectre.

Ok, I decided to transfer cells in other project (PROJ2 for facility).
In PROJ2 I did following actions:
1. Put reference to PROJ1 test_lib library in cds.lib file of PROJ2
2. Open Library Manager and copied  cells from PROJ1 test_lib library into PROJ2 test_lib library
3. Removed reference to PROJ1 test_lib from PROJ2 cds.lib file.

Maybe there is more smart approach to transfer cells between libraries, but I don't know it.

In anyway it doesn't work. Elaborator couldn't recognize transferred cells. What I should do - recreate manually all cells in PROJ2?

Regards.

Pavel.

.pak file is removed.

Now the situation is as follows:

icms-log:
Failed to elaborate ("90131BA_DIGITAL" "TB_0" "config").

ncelab.log:
ncelab: *E,NOUNIT: Unable to find a unit named '90131BA_DIGITAL' in the libraries.
ncelab: *E,NOUNIT: Unable to find a unit named '.TB_0:config' in the libraries.
ncelab: *E,NOUNIT: Unable to find a unit named '90131BA_DIGITAL' in the libraries.

TB_0 is the top-level testbench. It has schematic and config views. The last one I used to run simulation.
'90131BA_DIGITAL' is the library where all cells are situated.

What mean these elaborator errors?

Regards.

Pavel.

Finally the problem was resolved.
It was suffucient to put cmos_sch view before functional in HE view list.

So I succeded to simulate my design. But one incertitude stays.
When I was controlling execution I didn't see UltraSim in the list of processes (prstat utility), but only ncsim.
My actual design contains 2 parts - stimuli (coded in verilog) and digital part in the form of structural-gate transistor-level netlist from synthesis tool.

I thougt that ncsim is "responsible" for stimuli and UltraSim - for digital part.

Why I see only ncsim in the list of processes.

Regards.

Pavel.