Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
May 4
th
, 2024, 3:29pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Other CAD Tools
›
Physical Verification, Extraction and Analysis
› Assura: finding nets in layout
‹
Previous topic
|
Next topic
›
Pages: 1
Assura: finding nets in layout (Read 2942 times)
rho
New Member
Offline
Posts: 5
Belgium
Assura: finding nets in layout
Jun 21
st
, 2011, 4:57am
Is there a way to high-light a certain node in the layout after a successful Assura LVS run?
Ex. : I run an LVS on a layout and I know it contains a net XYX because it's in the schematic. Now I want to know were this specific net is in the layout.
Is there an easy way to do this?
Back to top
IP Logged
bernd
Senior Member
Offline
Posts: 229
Munich/Germany
Re: Assura: finding nets in layout
Reply #1 -
Jun 21
st
, 2011, 5:11am
This is possible with the Assura LVS Debug environment.
Design Window: Assura -> LVS Debug Env...
LVS Debug Env: Tools->Probe
* bernd
Back to top
Just another lonesome cad guy
IP Logged
rho
New Member
Offline
Posts: 5
Belgium
Re: Assura: finding nets in layout
Reply #2 -
Jun 21
st
, 2011, 5:29am
Works like a charm! Thanks.
I tried it before, but it seems I used the wrong syntax. At least you confirmed that it should work, and it does.
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
»» Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.