Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
May 4
th
, 2024, 5:19am
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Design
›
Mixed-Signal Design
› Clock divider.
‹
Previous topic
|
Next topic
›
Pages: 1
Clock divider. (Read 3799 times)
Jacki
Senior Member
Offline
Posts: 237
Clock divider.
Apr 02
nd
, 2014, 2:03pm
Hi,
I want to get a clock divider as shown in the figure, does anybody know how to do it with the basic digital logic blocks like DFF, AND gate, OR gate ...
Thank you.
Back to top
CLOCK.png
IP Logged
Jacki
Senior Member
Offline
Posts: 237
Re: Clock divider.
Reply #1 -
Apr 2
nd
, 2014, 2:07pm
The duty cycle is not 50%, I try to use clock divider by 5, or counter to achieve it, but I failed.
Back to top
IP Logged
AnalogDE
Senior Member
Offline
Posts: 137
Re: Clock divider.
Reply #2 -
Apr 2
nd
, 2014, 3:28pm
This looks pretty simple. You can do it with a counter with output logic that decodes the 'count'. Logic outputs a '1' when it hits its 'count' that it decodes. Run that logic and AND it with incoming clock... That should be it.
Back to top
IP Logged
Jacki
Senior Member
Offline
Posts: 237
Re: Clock divider.
Reply #3 -
Apr 2
nd
, 2014, 6:29pm
Hi AnalogDE,
Thank you very much for your reply. I don't follow you very well. I will make a test tomorrow. Could you show me a logic structure (building block) as you are convenient?
Back to top
IP Logged
Jacki
Senior Member
Offline
Posts: 237
Re: Clock divider.
Reply #4 -
Apr 3
rd
, 2014, 12:33pm
Hi AnalogDE,
I understand what you mean, thank you.
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
»» Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.