SNIKE
Junior Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/starblue.gif)
Offline
Posts: 27
|
Hi members, We have a System clock running at 120MHz, it has 300pS peak to peak jitter. :'( I am designing a pipeline ADC and my sampling frequency is 1MHz. I found that due to aperture uncertanity [jitter] my ADC's performance is limited.
Since my sampling frequency is much slower than my main noisy System clock, can I do somekind of filtering and create a new clean Clock? what other methods can I use to improve jitter at low frequencies?
Thanks in advance.
|