SNIKE
Junior Member
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Posts: 27
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Hi members, We have a System clock running at 120MHz, it has 300pS peak to peak jitter. :'( I am designing a pipeline ADC and my sampling frequency is 1MHz. I found that due to aperture uncertanity [jitter] my ADC's performance is limited.
Since my sampling frequency is much slower than my main noisy System clock, can I do somekind of filtering and create a new clean Clock? what other methods can I use to improve jitter at low frequencies?
Thanks in advance.
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