**cheap_salary wrote on Jan 18**^{th}, 2017, 2:17am:See Listing-1.

Your vco is not VCO.

Read documents surely.

VCO is Listing-4.

**Code:**`include “disciplines.vams”
module pll(out);
output out;
phase out;
parameter integer m = 1 from [1:inf); // input divide ratio
parameter real Kdet = 1 from (0:inf); // phase detector gain
parameter real Kvco = 1 from (0:inf); // VCO gain
parameter real c1 = 1n from (0:inf); // Loop filter C1
parameter real c2 = 200p from (0:inf); // Loop filter C2
parameter real r = 10K from (0:inf); // Loop filter R
parameter integer n = 1 from [1:inf); // feedback divide ratio
phase in, ref, fb;
electrical c;
oscillator OSC(in);
divider #(.ratio(m)) FDm(in, ref);
phaseDetector #(.gain(Kdet)) PD(ref, fb, c);
loopFilter #(.c1(c1), .c2(c2), .r(r)) LF(c);
vco #(.gain(Kvco)) VCO(c, out);
divider #(.ratio(n)) FDn(out, fb);
endmodule

In listing-1, how these definitions of the blocks know where I put the divider.va phaseDetector.va and so on?

I am not familiar with verilog-a either. thank you.

and when do simulation, I just simulate the single pll block in the schematic using noise analysis?