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how to build pll noise model based on verilog-a using Ken Kundert‘s method? (Read 11481 times)
lwzunique
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how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Jan 17th, 2017, 6:42pm
 
Hi,everyone.

I am beginner of PLL circuit design, recently I want to do analysis about the phase noise of PLL. and I found Ken Kundert's Paper:Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.
there are several problems  that confuse me so much.
1.if I want to copy your code about other listings, I have to put phase.vams into the directory the same as disciplines.vams, correct?
2.I can't compile the code for divider, the detail is shown bellow.

3.suppose that I have build all the blocks correctly, what should I do to have the overall phase noise, how to connect these blocks in the schematic in candence platform, and what simulation should I do,AC or Noise?

4.if I have get the phase noise data of all the blocks made by real process like TSMC or globafoundry. how
to build the verilog-a model to combine this noise data together to get the pll out's overall phase noise.

thanks everybody!

William
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cheap_salary
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #1 - Jan 17th, 2017, 10:54pm
 
lwzunique wrote on Jan 17th, 2017, 6:42pm:
1.if I want to copy your code about other listings, I have to put phase.vams into the directory the same as disciplines.vams, correct?
Correct, if you don't want to specify absolute path for "phase.vams".

However I recommend you to specify absolute path for "phase.vams" and place it in any directory.

lwzunique wrote on Jan 17th, 2017, 6:42pm:
2.I can't compile the code for divider, the detail is shown bellow.
What error do you get ?
Show us details.

lwzunique wrote on Jan 17th, 2017, 6:42pm:
3.suppose that I have build all the blocks correctly, what should I do to have the overall phase noise,
how to connect these blocks in the schematic in candence platform,
See Listing.18.
lwzunique wrote on Jan 17th, 2017, 6:42pm:
and what simulation should I do,AC or Noise?
Do Noise Analysis.

lwzunique wrote on Jan 17th, 2017, 6:42pm:
4.if I have get the phase noise data of all the blocks made by real process like TSMC or globafoundry.
how to build the verilog-a model to combine this noise data together to get the pll out's overall phase noise.
Adjust "n", "fc", "jitter", etc.

See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1275390599
http://www.designers-guide.org/Forum/YaBB.pl?num=1444923186
http://een.iust.ac.ir/profs/Abrishamifar/Analog%20Integrated%20Circuit%20Design/...
http://www.highfrequencyelectronics.com/index.php?option=com_content&view=articl...
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Ken Kundert
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #2 - Jan 18th, 2017, 1:13am
 
The syntax accepted by Verilog-AMS has changed somewhat over the years. In particular, apparently the way that you give array literals has changed. So the noise table should probably be given as ...
Code:
Theta(out) <+ noise_table_log('{
    1, n,
    bw, n,
    fmax, n*pow(fmax/bw), 2*order)
}, "dsn"); 



Notice the ' that initiates the array literal. Specifically, '{ ... }. Fixing that should probably clear up your syntax problem.

Also notice I switched to noise_table_log. That seems like that would probably be better than noise_table.

-Ken

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lwzunique
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #3 - Jan 18th, 2017, 2:06am
 
Quote:
Do Noise Analysis.

thanks @cheap_salary and Kundert, I have fixed the error in divider block, one part of the bracket was missing.
now i have built all the blocks, but the vco has no control terminal, as shown in the picture below, and I also don't know how to combine this blocks together?
[img][/img]
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cheap_salary
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #4 - Jan 18th, 2017, 2:17am
 
See Listing-1.
Your vco is not VCO.
Read documents surely.

VCO is Listing-4.
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lwzunique
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #5 - Jan 18th, 2017, 2:28am
 
cheap_salary wrote on Jan 18th, 2017, 2:17am:
See Listing-1.
Your vco is not VCO.
Read documents surely.

VCO is Listing-4.

Code:
`include “disciplines.vams”
module pll(out);
output out;
phase out;
parameter integer m = 1 from [1:inf); // input divide ratio
parameter real Kdet = 1 from (0:inf); // phase detector gain
parameter real Kvco = 1 from (0:inf); // VCO gain
parameter real c1 = 1n from (0:inf); // Loop filter C1
parameter real c2 = 200p from (0:inf); // Loop filter C2
parameter real r = 10K from (0:inf); // Loop filter R
parameter integer n = 1 from [1:inf); // feedback divide ratio
phase in, ref, fb;
electrical c;
oscillator OSC(in);
divider #(.ratio(m)) FDm(in, ref);
phaseDetector #(.gain(Kdet)) PD(ref, fb, c);
loopFilter #(.c1(c1), .c2(c2), .r(r)) LF(c);
vco #(.gain(Kvco)) VCO(c, out);
divider #(.ratio(n)) FDn(out, fb);
endmodule 


In listing-1, how these definitions of the blocks know where I put the divider.va  phaseDetector.va and so on?
I am not familiar with verilog-a either. thank you.
and when do simulation, I just simulate the single pll block in the schematic using noise analysis?
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #6 - Jan 18th, 2017, 2:45am
 
If you can not understand Verilog-A Language, can you understand Spectre or Spice Language ?

If you can understand either of Spectre or Spice Language, I can translate Lisiting-1 to them.

Verilog-A, Spectre and Spice are all circuit description languages.
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« Last Edit: Jan 18th, 2017, 7:12am by cheap_salary »  
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lwzunique
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #7 - Jan 18th, 2017, 3:05am
 
cheap_salary wrote on Jan 18th, 2017, 2:45am:
If you can not understand Verilog-A Language, can you understand Spectre or Spice Language ?

If you can understand either of Spectre or Spice Language, I can translate Lisiting-1 to them.

Verilog-A, Spectre and Spice are all circuit description langauges.


thanks@cheap_salary, I will study what your told me carefully and have a try. thank you.
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #8 - Jan 18th, 2017, 4:21am
 
Ken Kundert wrote on Jan 18th, 2017, 1:13am:
Notice the ' that initiates the array literal.
Specifically, '{ ... }.
At least, Cadence Spectre 14.1 don't show any warning even if without '.
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Ken Kundert
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #9 - Jan 18th, 2017, 4:00pm
 
The '{...} form is recommended in the latest Verilog-AMS LRM. It is something they picked up recently from SystemVerilog. This means that Verilog has two form for array literals, you can either use '{...} or {...}. The former represents packed arrays and the latter represents unpacked arrays. The '{...} form did not exist when Verilog-AMS first came out, so early versions of Verilog-AMS and Spectre only support the {...} form. I suspect that the more recent versions of Spectre are requiring the use of the '{...} form when specifying the array values to the laplace, zi, and table functions.

-Ken
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lwzunique
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #10 - Jan 18th, 2017, 7:46pm
 
I have built the schematic as shown below,but i don't know how to get the phase noise output.

I do the noise simulation, but the output curve is not as shown in the paper:Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #11 - Jan 18th, 2017, 7:51pm
 
another problem is that, I want to simulate the noise of single VCO block, it can't work.
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #12 - Jan 18th, 2017, 8:00pm
 
You don't reflect listing-1 at all.
Surely see listing-1.
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #13 - Jan 18th, 2017, 8:24pm
 
really sorry for my mistake.
now I think it is right.
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Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Reply #14 - Jan 18th, 2017, 8:36pm
 
Do you surely set nonzero value noise ?
If n is equal to zero, noise is not generated.
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