I do not know which random function could I use. The random functions in VerilogA require a seed. Generating a random seed will have the same problem as I already have.
I've looked in different ways as well, but to no avail:
I haven't found a way to call a system function. I tried using the $simparam("systime") as a seed, but its resolution (1sec) wasn't random at all.
I also have not found (yet) a reliable way in our flow to execute a script between netlisting and simulation to insert a random value.
Therefore I would very grateful for any small working example.
Here is an example of mine:
Code:`include "discipline.h"
`include "constants.h"
module rand_bit_simple (vout);
output vout;
electrical vout;
parameter integer seed = 21;
integer var_seed;
integer rnd;
analog begin
@ (initial_step) begin
var_seed = seed; // variable is needed; updated after every step
rnd = $random(var_seed);
end // initial step
V(vout) <+ rnd*1e-12;
end //analog
endmodule