Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
How to make Cadence plot output expression in new subwindow	jqjqjq	0	390	Jun 1^st, 2013, 4:29am By: jqjqjq
Breaking loop with for stb analysis	RobG	1	1836	May 29^th, 2013, 5:05am By: Frank Wiedmann
ocean script	Evgenii	1	2548	May 23^rd, 2013, 2:50am By: boe
Monte Carlo simulation methodology	AS	4	5332	May 15^th, 2013, 4:43pm By: AS
Moved: LVS error: bad component sub type - Started by: mixed_signal This Topic has been moved to Physical Verification, Extraction and Analysis by Ken Kundert
Monte carlo simulation types with corners using spectre,ADEXL options	yvkrishna	5	1524	Apr 27^th, 2013, 11:06am By: yvkrishna
Unable to attach technology library?	emax00	0	1791	Apr 18^th, 2013, 8:00pm By: emax00
.cdsinit not being read at startup.	Sharath Raju	0	1584	Apr 15^th, 2013, 12:29am By: Sharath Raju
NCSU FreePDK45 problem	emax00	0	1600	Apr 14^th, 2013, 11:06pm By: emax00
Dynamic, Short circuit power power consumption of CMOS inverter	nvrk	9	7687	Mar 25^th, 2013, 9:12pm By: nvrk
How to simulate Gated Ring Oscillator?	akash9183	0	1779	Mar 25^th, 2013, 3:56am By: akash9183
Stb analysis	uncle_ezra	3	1030	Mar 23^rd, 2013, 5:06am By: threepwood
Different op amp open loop gains from analysis	batmanbeginz	3	3875	Mar 21^st, 2013, 1:22am By: raja.cedt
Spectre dying	padawan	2	2354	Mar 20^th, 2013, 10:11am By: padawan
Using .PLOT in ngspice	simsim	0	7870	Mar 12^th, 2013, 11:39pm By: simsim
32kHz crystal « Pages 1 2 »	ic_engr	17	676	Mar 12^th, 2013, 12:08pm By: ic_engr
Python script to transfer ADE-XL output to Excel file	acbalbason	0	1380	Mar 12^th, 2013, 11:08am By: acbalbason
VerilogA writing to text file	jjrice	1	2555	Mar 12^th, 2013, 8:36am By: Geoffrey_Coram
Monte carlo simulation in Cadence IC6.1.5	bhl3302	1	131	Mar 6^th, 2013, 3:28pm By: sheldon
Moved: Assura RCX fails with Generic PDK 45nm - Started by: kmmankad This Topic has been moved to Physical Verification, Extraction and Analysis by Ken Kundert

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