Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
about sigma-delta modulator	seamus	1	2432	Jan 18^th, 2007, 5:59pm By: beargebinjie
Moved: simulation after Place&Route - Started by: Forum Administrator This Topic has been moved to Physical Verification, Extraction and Analysis by Forum Administrator.
sigma delta modulator for pll	Esther	1	2406	Jan 17^th, 2007, 12:51am By: adesign
Hogge phase detector	Visjnoe	3	7303	Jan 15^th, 2007, 12:06pm By: mg777
the noise simulation of switch capacitor filter.	holmes	1	2210	Jan 15^th, 2007, 7:38am By: Andrew Beckett
ADC clock jitter specification	Visjnoe	11	10429	Jan 14^th, 2007, 12:40pm By: mg777
good paper on noise analysis of CDS circuits	vivkr	4	3650	Jan 12^th, 2007, 2:39am By: vivkr
Verilog-A model for comparator	cat18521	2	1174	Jan 11^th, 2007, 2:24pm By: cat18521
synopsys DC ungroup	qlmei	0	1706	Dec 25^th, 2006, 8:39pm By: qlmei
powerup/down time	dandelion	1	1799	Dec 25^th, 2006, 1:43am By: ywguo
about VCO modeling	jeffyan	3	2899	Dec 25^th, 2006, 1:38am By: ywguo
Clock Duty Cycle Correction Circuit	sachinagg	13	14364	Dec 21^st, 2006, 3:54am By: jeffyan
problem in Charge pump design	Esther	6	6977	Dec 21^st, 2006, 3:32am By: jeffyan
two stage ring vco question?	email_gz	4	4252	Dec 20^th, 2006, 6:16pm By: email_gz
Charge Pump DC/DC Converter Stability!	stephen_chou	8	1699	Dec 13^th, 2006, 10:46pm By: stephen_chou
MOS flicker noise inversely proportional to WL ?	Hunter_BJUT	4	5274	Dec 10^th, 2006, 2:56am By: Hunter_BJUT
freq_meter component in ahdlLib	adesign	3	3318	Dec 8^th, 2006, 2:51pm By: Ken Kundert
Digital PLL jitter performance	adesign	0	336	Dec 8^th, 2006, 9:33am By: adesign
Random data signal in cadence	rjshmadala	10	18549	Dec 3^rd, 2006, 8:36pm By: jbdavid
PFD reset path mismatch	neoflash	9	9293	Nov 27^th, 2006, 12:38pm By: loose-electron

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