Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
uniform distribution in verilog A	josef_sous	3	3517	Jan 22^nd, 2015, 1:38pm By: Geoffrey_Coram
Paramset selection based on temperature	ee2	3	3233	Jan 20^th, 2015, 1:30pm By: Geoffrey_Coram
setting an initial voltage for a VeriologA capacitor	rosadellavita	2	4103	Jan 5^th, 2015, 1:06pm By: Geoffrey_Coram
fixed time step in Verilog-A?	fgcsk	2	3177	Nov 22^nd, 2014, 11:54pm By: fgcsk
how to delay a signal	jagadeesh	2	2849	Nov 14^th, 2014, 5:21am By: Ken Kundert
PRBS-7 data source for generation of 5 and 10 GBPS	J_im	1	2343	Nov 13^th, 2014, 10:43am By: Geoffrey_Coram
Getting information about convergence of internal nodes	Prasad Sarangapani	1	1777	Nov 13^th, 2014, 10:33am By: Geoffrey_Coram
special file names in Verilog-A	sutapanaki	1	557	Nov 13^th, 2014, 10:30am By: Geoffrey_Coram
VPI within analog section	Fabian H.	0	1888	Oct 17^th, 2014, 8:39am By: Fabian H.
Expand Verilog Compiler Directives	cheap_salary	0	1378	Oct 15^th, 2014, 4:07am By: cheap_salary
Blocking assignment working as a non-blocking....	paul miller	7	5691	Oct 13^th, 2014, 3:33am By: boe
A stimulus for digital signal using verilog-A	ywguo	5	1341	Oct 6^th, 2014, 9:33pm By: ywguo
mixing spice and VerilogA	jmith	5	4549	Oct 1^st, 2014, 1:51am By: boe
How to make a 1:4 demux in VAMS	wag_master	8	2062	Sep 26^th, 2014, 3:30pm By: wag_master
verilog-A dependent source NOT converge	ywguo	3	3558	Sep 24^th, 2014, 2:06am By: boe
sigma delta modulator	optimized	11	17052	Sep 22^nd, 2014, 8:24pm By: cheap_salary
Verilog-A speed in Spectre	omar	7	2287	Sep 6^th, 2014, 11:49pm By: Ken Kundert
Verilog-A defined units in Spectre	adelaid	1	1944	Sep 3^rd, 2014, 10:45am By: boe
OR Model	bki	2	2159	Aug 22^nd, 2014, 10:31am By: Ken Kundert
Problem on simulating VerilogA comparator model with PSS analysis	AMSA	3	3407	Aug 20^th, 2014, 10:47am By: Ken Kundert

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