Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Maybe a stupid question	Ciprian	4	3050	Aug 19^th, 2014, 10:45am By: Ken Kundert
Verilog-A Model	bki	3	1182	Aug 18^th, 2014, 7:31am By: bki
speeding up mixed-signal simulations	alirezad	0	429	Jul 14^th, 2014, 5:35pm By: alirezad
$dist_normal	fullstop	5	6619	Jul 8^th, 2014, 7:58am By: Geoffrey_Coram
Simulation Speed in verilogams: Digital Context versus Analog Context	Zorro	1	484	Jul 8^th, 2014, 7:53am By: Geoffrey_Coram
initial_step for dc sweep	dilbert	3	4156	Jul 8^th, 2014, 7:46am By: Geoffrey_Coram
Using Parameters in VerilogA and VerilogAMS	Srinivas_BS	4	3009	Jul 8^th, 2014, 7:45am By: Geoffrey_Coram
verilog-A syntax for a capacitor or resistor	bigball	2	3647	Jul 8^th, 2014, 7:23am By: Geoffrey_Coram
How to use @(final_step) inside the digital context in verilogams	Zorro	1	3048	Jun 26^th, 2014, 9:21pm By: Srinivas_BS
Changing clk period dynamically	satvika	1	1571	Jun 26^th, 2014, 9:17am By: boe
In what case we mixed analog and digital in Verilog-AMS?	sharpmental	2	2053	Jun 20^th, 2014, 5:59pm By: Ken Kundert
synchronize apb bus	sapir	0	1143	Jun 19^th, 2014, 5:15am By: sapir
differential clock d flip flop verilog-a model	mahesh venkatt	1	2550	May 9^th, 2014, 7:20am By: boe
$random always generates the same value	Lucho	3	5099	Apr 16^th, 2014, 10:51am By: Geoffrey_Coram
Transition Filter DC operation	s1s2kim	1	2419	Apr 8^th, 2014, 12:25am By: Ken Kundert
transition function in Verilog-A	prcken	2	3974	Apr 5^th, 2014, 2:14pm By: prcken
Parent Child Instantiation	Davivilla	5	8205	Mar 27^th, 2014, 8:46am By: Davivilla
Problem with Analog Sensitivity to Digital Events	Zorro	14	12864	Mar 13^th, 2014, 4:39pm By: Ken Kundert
Need Verilog A model for Fully differential OTA	siegi	5	8578	Mar 6^th, 2014, 6:21am By: eelxpeng
Simulating Verilog-A and Verilog-D together	mowiehowie	1	2447	Feb 28^th, 2014, 9:40am By: Andrew Beckett

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