Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
how to minimize the bias circuit's effect to LC VCO's phase noise	anny	7	6014	Jan 2^nd, 2010, 11:50pm By: rfcooltools.com
Moved: How to simulate the IIP2 in DCR down mixer? - Started by: zzhuang This Topic has been moved to RF Simulators by Ken Kundert
RF circuit Dc bias question	liletian	6	6733	Dec 15^th, 2009, 8:12pm By: RFICDUDE
Multiple Antenna GPS	daver	0	1196	Dec 10^th, 2009, 12:52pm By: daver
RSSI settling time for a direct-conversion receiver	aaron_do	0	1481	Dec 2^nd, 2009, 7:33pm By: aaron_do
Clock buffer in PLL	raja.cedt	5	5123	Nov 30^th, 2009, 9:25am By: loose-electron
questions about noise figure for mixers	eecs4ever	3	4628	Nov 20^th, 2009, 11:07pm By: pancho_hideboo
How to model the parasitics for input and output pins at a freq. of 1GHz.	pkd	4	4547	Nov 19^th, 2009, 4:09pm By: ci
Crest Factor v/s PAPR	sandman	9	10214	Nov 13^th, 2009, 1:12am By: pancho_hideboo
QFN48: maximum die size	Faisal	5	1181	Nov 12^th, 2009, 5:51pm By: loose-electron
differential current source	harryhu	0	1296	Nov 7^th, 2009, 9:47pm By: harryhu
Matching Networks	aaron_do	5	4124	Nov 6^th, 2009, 10:21am By: loose-electron
good quality off-chip inductor problem?	liletian	4	4275	Nov 6^th, 2009, 6:40am By: RFICDUDE
Separate supplies for PLL blocks	boa	11	8811	Nov 4^th, 2009, 4:13am By: Mayank
tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design	ReadWDX	4	5348	Nov 3^rd, 2009, 7:19am By: Mayank
How to design an antenna, from one-port device to two-port device?	Jack	2	4908	Nov 2^nd, 2009, 11:13pm By: pancho_hideboo
what is active S-paramter, and passive S-paramter?	Jack	1	2449	Nov 2^nd, 2009, 11:09pm By: pancho_hideboo
NF min of a device	analog_cha	3	3326	Nov 2^nd, 2009, 7:09pm By: RFICDUDE
Impedance matching RX/TX: 3dB power loss?	Visjnoe	5	4765	Nov 2^nd, 2009, 10:27am By: Visjnoe
Moved: Multi-carrier simulation - Started by: sandman This Topic has been moved to RF Simulators by Ken Kundert

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