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Subject	Started by	Replies	Views	Last post
Nfet in Nwell capacitance?	joel	1	2883	Jan 3^rd, 2008, 2:57am By: Terence
single layer oxide deposition process	vivkr	6	5704	Nov 29^th, 2007, 10:20pm By: Berti
MOSIS ring oscillator test structure	jeremy	2	3294	Nov 28^th, 2007, 3:15am By: krishnap
BSIM: System of Units	tariavo	5	5122	Nov 27^th, 2007, 6:52am By: tariavo
drain capacitance calculations	jefkat	2	2795	Nov 16^th, 2007, 1:02am By: jefkat
vbic HBT rth & cth conversion SpectreRF to HSPICE	imtired	2	3197	Nov 12^th, 2007, 6:24pm By: imtired
Spectre Model for High Voltage MOS	k-one	8	11391	Nov 6^th, 2007, 4:03am By: k-one
Temperature optimization of BSIM Parameters	Mooraka	4	4197	Oct 10^th, 2007, 4:43am By: simon2
Any implementation of of FinFET devices	krishnap	2	3168	Oct 10^th, 2007, 12:28am By: krishnap
HSPICE or Spectre	Nano_Model	3	3813	Sep 29^th, 2007, 7:17am By: Visjnoe
Bandgap (Si, Ge, etc.) variation with temp/pressur	vivkr	0	1700	Sep 20^th, 2007, 2:01am By: vivkr
process variation of BJT Vbe	vivkr	6	1403	Sep 20^th, 2007, 1:55am By: vivkr
RF modeling	modelinger	2	607	Sep 17^th, 2007, 11:28pm By: 337see733
How is Vth defined?	fran2k5	2	2923	Aug 8^th, 2007, 5:38am By: fran2k5
Max. Vds for 3.3V pMOS in 0.18um CMOS process	Terence	2	3447	Aug 1^st, 2007, 11:14pm By: krishnap
BJT storage time in turn-off transient	insider	0	2669	Jul 11^th, 2007, 9:31pm By: insider
Strain & mobility	mg777	4	4201	May 23^rd, 2007, 6:56am By: krishnap
Plotting Vth variations	Croaker	11	9983	Mar 20^th, 2007, 5:44am By: Croaker
Moved: Plotting/Printing MOS DC Params in Cadence - Started by: Forum Administrator This Topic has been moved to Entry Tools by Forum Administrator.
floating gate mos transistor verilog	CadenceUser888	1	2696	Mar 14^th, 2007, 10:49am By: Geoffrey_Coram

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