Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
`include search path questions	danmc	1	2411	Aug 14^th, 2013, 10:02am By: boe
how to attach verilog-AMS to a technology model file (0.18um or 65nm)	susona	0	1386	Aug 4^th, 2013, 10:08pm By: susona
can we do the INL and DNL measurements with verilog-AMS code	susona	0	1477	Aug 4^th, 2013, 9:09pm By: susona
trouble in simulating verilog-AMS code using Virtuoso ADE	susona	2	712	Aug 2^nd, 2013, 9:32am By: susona
Modeling Gm(t) of a hard-limiter Voltage to Current converter.	Ricky Chen	1	515	Aug 2^nd, 2013, 8:51am By: Geoffrey_Coram
parameters in analog function	spinfab	3	3361	Aug 2^nd, 2013, 8:48am By: Geoffrey_Coram
Verilog-A compiler directive question	danmc	1	2030	Aug 2^nd, 2013, 8:45am By: Geoffrey_Coram
Modelling a White-Cyclostaionary Current Noise source in VerilogA	Ricky Chen	1	2083	Jul 23^rd, 2013, 12:53pm By: Geoffrey_Coram
resistor change using veriloga	sen	1	2082	Jul 23^rd, 2013, 12:48pm By: Geoffrey_Coram
switch model in DC-sweep analysis	spinfab	2	2639	Jul 22^nd, 2013, 2:04am By: spinfab
Where to start for Verilog AMS?	visbi	3	2933	Jul 18^th, 2013, 12:40am By: Frank Wiedmann
Monte-Carlo simulation and writing to file from VerilogA	sutapanaki	1	578	Jul 15^th, 2013, 7:15am By: boe
Problem in creating logic to electrical connect module in verilogams	indra0804	1	2600	Jul 15^th, 2013, 7:08am By: boe
Help required for understanding OP-AMP Verilog AMS code	indra0804	3	3965	Jul 8^th, 2013, 6:34am By: indra0804
time step management	spinfab	3	3196	Jul 5^th, 2013, 10:59am By: Ken Kundert
veriloga code of a switch	jovial	5	8099	Jun 25^th, 2013, 8:53am By: boe
Error during simulation	fuzail	1	2039	Jun 16^th, 2013, 12:54pm By: rfidea
Veriloga coding of fully differential opamp	fuzail	4	12858	Jun 3^rd, 2013, 3:12am By: ali_kourani
How to Generate a Rectangular Pulse with Different Amplitudes	Kevin Finn	4	3905	Jun 3^rd, 2013, 2:10am By: Kevin Finn
getting pulse width	spinfab	2	2403	May 28^th, 2013, 12:56pm By: spinfab

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