Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Usage of wreal	Ankur.Chaplot	4	5301	Jun 29^th, 2008, 5:33pm By: Jess Chen
power supply noise model	Alok519	0	1398	Jun 26^th, 2008, 2:37am By: Alok519
how to realize a time-varying signal in verilog-a	wwm101	2	2177	Jun 24^th, 2008, 6:03am By: wwm101
About the error " internal timestep is too small"	icsoul	8	5723	Jun 23^rd, 2008, 5:04am By: icsoul
Interpolation in Verilog-A	Alok519	3	922	Jun 22^nd, 2008, 4:50am By: Alok519
questions on transition filter	veriloganewbie	10	7821	Jun 20^th, 2008, 8:10am By: Geoffrey_Coram
Issues in simulatingwith spectre-verilog simulator	paddu	1	3705	Jun 19^th, 2008, 1:43pm By: jbdavid
model of counter (Verilog-A)	mus	1	908	Jun 19^th, 2008, 9:45am By: jbdavid
Two questions about verilog-A	icsoul	4	3683	Jun 15^th, 2008, 9:28pm By: icsoul
How to calculate the freq of the signal with vams?	icsoul	3	3020	Jun 13^th, 2008, 6:58am By: Geoffrey_Coram
Absdelay function implementation	lobarth	3	4068	Jun 12^th, 2008, 6:59am By: lobarth
Delay in Verilog-A	ssdfz	7	2702	Jun 1^st, 2008, 4:37am By: ywguo
Hierarchical VerilogA for Cadence Spectre/AMS	designerjoe	2	5732	May 29^th, 2008, 3:19am By: designerjoe
Idiot's Guide to mixed-mode verilog?	joel	1	2200	May 27^th, 2008, 1:58pm By: joel
current limiter in Verilog-A	icdes321	4	1270	May 27^th, 2008, 11:54am By: Ken Kundert
VerilogA simulation time	ssdfz	10	2364	May 23^rd, 2008, 4:58am By: Geoffrey_Coram
Best book to learn Verilog?	arjunpcet	4	194	May 20^th, 2008, 8:54pm By: arjunpcet
Question about SH VerilogA model	bmwsky	3	3222	May 16^th, 2008, 12:16pm By: Ken Kundert
problem with transition filter in verilogA	ssdfz	5	8214	May 14^th, 2008, 11:25am By: ssdfz
user-defined disciplines and natures	engelbrl	2	793	May 5^th, 2008, 10:40pm By: engelbrl

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