Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
ADC two step converter	solanojedi	1	3300	Feb 2^nd, 2011, 6:09am By: Marq Kole
analog module instantiation in Verilog AMS	priyanka	8	63029	Dec 8^th, 2010, 2:33am By: priyanka
Debugger for VerilogA	SAM_K	2	3914	Dec 1^st, 2010, 10:14am By: Ken Kundert
About PSPICE model for tps2817	dani86	2	2960	Dec 1^st, 2010, 8:27am By: Geoffrey_Coram
diode	SAM_K	2	2964	Nov 8^th, 2010, 7:30am By: jerome_ams
Typical Audio, CD quality Anti aliasing filter	Fernando	3	4449	Nov 7^th, 2010, 9:35am By: buddypoor
Thevenin Eq. Model	samiran	1	2566	Nov 3^rd, 2010, 7:46am By: Ken Kundert
A high side non-ideal current mirror in Verilog-A?	the_wavefunction	6	7576	Oct 27^th, 2010, 9:05am By: the_wavefunction
Looking for OSCillator or VCOscillator models useable in Spectre-RF PSS-pnoise,	ppg	1	87	Sep 27^th, 2010, 1:45am By: Ken Kundert
Analog PLL Modeling	Rajeev	0	1958	Sep 24^th, 2010, 11:13am By: Rajeev
Transient simulation of PLL in Phase-Domain possible?	ussmueller	2	3459	Sep 10^th, 2010, 7:42pm By: Eugene
ac small-signal simulation of a magnetics behavioral model	engelbrl	5	5888	Sep 9^th, 2010, 9:29pm By: Ken Kundert
voltage dependent capacitor model	vivkr	13	3107	Aug 12^th, 2010, 1:06pm By: Mihir Mudholkar
problems about bidirectional pin	bsaqycx	2	116	Aug 11^th, 2010, 8:30pm By: bsaqycx
cannot filter out short pulses	Pavel	2	767	Aug 3^rd, 2010, 10:37am By: Ken Kundert
Model for offset of latch	Parveen	2	2834	Jul 23^rd, 2010, 1:56am By: raja.cedt
problem with detecting falling edge	mowiehowie	1	2359	Jul 22^nd, 2010, 12:12pm By: Geoffrey_Coram
clock generator in Verilog-A	bsaqycx	4	9831	Jul 19^th, 2010, 12:54am By: bsaqycx
Modeling of Arbitrary Phase Shift in Verilog-A	samiran	3	6324	Jun 24^th, 2010, 11:38am By: pancho_hideboo
probing external current from subckt enclosed bsource expression	Kalimero	1	2614	Jun 6^th, 2010, 5:41am By: Kalimero

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