Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
time constant doubt	singh	4	971	Nov 23^rd, 2011, 2:42am By: singh
windowed integrator	NTR	1	2440	Nov 21^st, 2011, 2:36pm By: loose-electron
How to start modeling?	RKGARG	1	2192	Nov 17^th, 2011, 5:57am By: Geoffrey_Coram
PLL loop parameters	pumba007	3	3793	Nov 5^th, 2011, 1:14pm By: loose-electron
integrator abnormal behavior	NTR	7	5836	Oct 28^th, 2011, 2:01am By: boe
First order GmC integrator	NTR	5	5254	Oct 27^th, 2011, 3:46am By: boe
voltage limited current source	danmc	5	1321	Aug 19^th, 2011, 8:36am By: danmc
phase noise simulation	kunhsun	2	3728	Jul 8^th, 2011, 9:57am By: kunhsun
Bimodal distribution of Oscillator Jitter in Verilog A	Praveen K	0	3001	Jun 29^th, 2011, 4:46am By: Praveen K
concatenate operation	samy	4	4121	Jun 17^th, 2011, 9:12am By: samy
Verilog A model for PRBS N bit	AnkurVerigy	1	8580	Jun 16^th, 2011, 11:50am By: boe
VCO code for PLL (possible timer issues)	SJ	0	2317	Jun 9^th, 2011, 11:58am By: SJ
Trouble writing VerilogA model for a circuit block with vdd! input pin	SJ	1	2909	May 27^th, 2011, 10:10am By: boe
model digital accumulator gain in matlab?	supermoment	0	2843	Apr 18^th, 2011, 3:18am By: supermoment
SINC verilog-A modeling	usr	0	2365	Apr 8^th, 2011, 7:22am By: usr
Timing constraint and $recovery system task	Patislas	5	4813	Apr 5^th, 2011, 11:25am By: boe
some questions when making IBIS model of LVDS driver ?	DP_Design	0	2600	Mar 29^th, 2011, 11:12pm By: DP_Design
Bidirectional shift register: continuous time modelling in Verilog A	mrxyzlinkoping	11	15088	Mar 13^th, 2011, 12:45pm By: mrxyzlinkoping
How can I simulate sampling jitter in simulink?	ray_wang	2	5308	Mar 3^rd, 2011, 2:14pm By: love_analog
gates.va and transition()	Geoffrey_Coram	10	14371	Feb 24^th, 2011, 5:43pm By: naderi

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