Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
no connection module found!!	shirin_br	1	4061	Jan 16^th, 2008, 6:16am By: rajdeep
concurrency semantics in VerilogA	rajdeep	7	1493	Jan 10^th, 2008, 11:21am By: rajdeep
Verilog-ams tool	rite2rajeev	3	3485	Jan 8^th, 2008, 5:37am By: rite2rajeev
parameterize the dimension of variables	Aigneryu	5	3928	Dec 21^st, 2007, 1:00pm By: Aigneryu
How to build D-Latch in verilogA without hidden st	AlexT	2	2842	Dec 17^th, 2007, 2:01pm By: seefree
how to modeling a full differential opamp ?	zhujun134	2	2722	Nov 30^th, 2007, 1:40pm By: jbdavid
Array declaration for analog output	shaikhsarfraz	1	2528	Nov 30^th, 2007, 1:38pm By: jbdavid
Help with Verilog -A：bandpass lna	surer	2	6077	Nov 28^th, 2007, 4:41pm By: surer
Help with Verilog : Cordic Code Posted.	dash82	0	2082	Nov 24^th, 2007, 8:13pm By: dash82
Instantiating a model in Verilog-A	IVerify	1	2077	Nov 15^th, 2007, 11:27am By: IVerify
How can I use the model in the modeling	pxddt	1	2042	Nov 8^th, 2007, 2:22am By: bernd
Instantiating a Spectre source in Verilog-A	Croaker	2	2883	Nov 7^th, 2007, 11:27am By: Croaker
counter	kamath	2	2952	Oct 31^st, 2007, 6:58am By: Geoffrey_Coram
Help needed for modelling a sensor block in VAMS	shaikh_sarfraz	3	3497	Oct 30^th, 2007, 11:37am By: Geoffrey_Coram
VPI function for analog signals	at	0	1512	Oct 25^th, 2007, 1:00pm By: at
$monitor -- Verilog Problem.	dash82	0	1484	Oct 24^th, 2007, 12:56pm By: dash82
Verilog - Race Condition - Please Help !!	dash82	0	1529	Oct 24^th, 2007, 12:33am By: dash82
Limitation with Cadence AMS designer suite	shaikh_sarfraz	1	2742	Oct 23^rd, 2007, 1:42pm By: Ken Kundert
syntax error for string parameter	lily	2	2940	Oct 11^th, 2007, 6:41pm By: lily
Need to use a pin named "I"	IVerify	2	3818	Oct 3^rd, 2007, 12:09pm By: IVerify

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