Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
question about the connectRules	Aigneryu	2	2516	Apr 7^th, 2007, 7:09pm By: Aigneryu
why variable to branch incorrectly? help!	yamamaya	7	4818	Apr 6^th, 2007, 12:23pm By: Geoffrey_Coram
How to model frequency domain in Verilog-A	Bill Toole	1	1935	Apr 5^th, 2007, 5:51pm By: Ken Kundert
Problem of verilog-ams in Spectre	smchiu	3	4103	Apr 5^th, 2007, 5:33am By: Geoffrey_Coram
entity/architecture	aldavis	6	5049	Apr 4^th, 2007, 2:15am By: jbdavid
How do I force DFF state to zero @ initial step?	gabe	2	2170	Mar 29^th, 2007, 8:13am By: gabe
Can VerilogA input Hexadecimal number?	seefree	2	2793	Mar 29^th, 2007, 5:49am By: seefree
Pll phase freq detector that clamps?`	davith	0	1102	Mar 19^th, 2007, 12:50pm By: davith
AHDL models for Comparator Offset Simulation Paper	Croaker	0	1371	Mar 18^th, 2007, 4:43pm By: Croaker
random PWM	trond	3	741	Mar 17^th, 2007, 5:11pm By: jbdavid
Adding phase noise in the VCO model	Amit Singh	1	2052	Mar 15^th, 2007, 1:27pm By: Ken Kundert
verilog build-in functions manual user guide	ihabraad	2	2439	Mar 15^th, 2007, 6:56am By: Andrew Beckett
Load and save command in spectre?	Amit Singh	1	1677	Mar 15^th, 2007, 6:48am By: Andrew Beckett
basics for verilog-A and vhdl-ams ?	richard88	1	1762	Mar 13^th, 2007, 7:38am By: Geoffrey_Coram
Printing Instance name in Ultrasim	Venkateshr	1	1557	Mar 13^th, 2007, 7:25am By: Geoffrey_Coram
Frequency lock in CDR	Amit Singh	0	1296	Mar 11^th, 2007, 4:49am By: Amit Singh
Saturating amplifier following VCO	Amit Singh	0	1482	Mar 10^th, 2007, 5:20pm By: Amit Singh
Passing variables to laplace_nd	Saran	6	10607	Mar 6^th, 2007, 6:30am By: Saran
Frequency change measurement in time domain	Amit Singh	1	770	Mar 5^th, 2007, 11:03am By: Andrew Beckett
NAND gate, multiple input module, gate cap?	altaj	12	9112	Mar 5^th, 2007, 5:43am By: Geoffrey_Coram

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