Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Hi	VerHDL	0	1265	Jan 5^th, 2007, 10:20pm By: VerHDL
transform stimuli from Spice	Pavel	2	2434	Jan 2^nd, 2007, 5:49am By: Pavel
Verilog A	kkjupally	3	3228	Dec 25^th, 2006, 1:28am By: sheldon
Reading MATLAB into VerilogA	makelo	3	81	Dec 11^th, 2006, 4:36pm By: Jess Chen
Synthesis Problem With Capture Program	EEStyx	2	1726	Dec 11^th, 2006, 9:54am By: EEStyx
array initialization in Verilog	Pavel	2	3497	Dec 9^th, 2006, 10:03am By: Ken Kundert
VCO model understanding	neoflash	4	4439	Dec 9^th, 2006, 10:01am By: Ken Kundert
help debug this random noise gen code	neoflash	5	6567	Dec 9^th, 2006, 9:28am By: Ken Kundert
Any PC based simulator for verilog AMS?	neoflash	6	1371	Dec 8^th, 2006, 11:18pm By: jbdavid
Help Required for Veriloga Code of NAND gate	junaidgill	4	8143	Nov 29^th, 2006, 12:13am By: Ken Kundert
verilogA error: ARnow: Undefined variable.	xter	3	5471	Nov 27^th, 2006, 8:41am By: xter
Moved: Question on Jitter Tolerance Pattern Gen Code - Started by: Forum Administrator This Topic has been moved to VHDL-AMS by Forum Administrator.
[q] in simulating verilog-a in hspice	kidhyun	3	3253	Nov 21^st, 2006, 5:58am By: Geoffrey_Coram
Gaussian Noise Source	Kudie	2	4567	Nov 21^st, 2006, 4:25am By: Kudie
Difference between voltage and electrical	neoflash	1	499	Nov 20^th, 2006, 4:33am By: Geoffrey_Coram
how we probe local variables in verilog-A sim	neoflash	2	3186	Nov 18^th, 2006, 6:15am By: neoflash
Simultaion under ADvance MS	skagoods	0	1330	Nov 17^th, 2006, 10:20am By: skagoods
How to chose seed?	neoflash	5	4844	Nov 17^th, 2006, 5:54am By: Geoffrey_Coram
coffee maker problem	lanun_kampung	3	4166	Nov 10^th, 2006, 5:07am By: Geoffrey_Coram
Connect Modules	tushit	0	1267	Nov 8^th, 2006, 10:46am By: tushit

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