Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
[q] verilog-a in hspice	kidhyun	1	2031	Nov 8^th, 2006, 10:27am By: Geoffrey_Coram
Generate a task	Pinhead	0	1190	Nov 8^th, 2006, 5:55am By: Pinhead
Inout port problem	stumcn	0	1444	Nov 8^th, 2006, 4:11am By: stumcn
Set Parameters with Variables ?	Pinhead	2	2435	Nov 6^th, 2006, 11:15pm By: Pinhead
instantiating a module	xter	2	2391	Nov 6^th, 2006, 7:05am By: Pinhead
IS there any training class or doc on Verilog-AMS?	neoflash	1	2036	Nov 6^th, 2006, 6:08am By: Geoffrey_Coram
wreal	Eugene	0	2052	Nov 3^rd, 2006, 2:29pm By: Eugene
help me with simulation of ac	spectre	0	1313	Nov 2^nd, 2006, 10:56pm By: spectre
Variable Gain with table_model	bessib	4	80	Nov 2^nd, 2006, 8:39pm By: Ken Kundert
from verilog-ams to verilog-hdl	douglas	1	1962	Oct 30^th, 2006, 7:59am By: Eugene
Verilog-A design flow question	lrc	6	1387	Oct 28^th, 2006, 1:53pm By: Andrew Beckett
VerilogA code for instance name and read write fil	CadenceUser888	5	7122	Oct 25^th, 2006, 3:26am By: CadenceUser888
Is this a bug of Ken's vco vams model?	greatqs	2	2889	Oct 23^rd, 2006, 9:03am By: Ken Kundert
Any Guide for Dummy in Coding Verilog A ?	337see733	8	7960	Oct 22^nd, 2006, 10:17am By: jbdavid
Digital gates in Verilog-A	cr	7	6531	Oct 18^th, 2006, 10:20am By: cr
model of capacitor, controlled with voltage need	stary	7	5289	Oct 9^th, 2006, 8:06am By: Ken Kundert
pwm in verilog	uzma	3	5088	Sep 30^th, 2006, 2:09am By: jbdavid
What is $Vt for a ordinary diode in veriloga code	gmadhavareddy	5	5138	Sep 30^th, 2006, 1:52am By: jbdavid
many modules in one cell (Virtuoso-AMS)?	Pavel	2	2394	Sep 30^th, 2006, 1:36am By: jbdavid
Quick reference guide to Verilog-A	Dave Dobson	4	3636	Sep 30^th, 2006, 1:17am By: jbdavid

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