Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Please help	2raghu	4	82	Sep 15^th, 2006, 8:43am By: Geoffrey_Coram
Mixed signal simulation time	mady79	2	2253	Sep 13^th, 2006, 10:44am By: jbdavid
IC analysis	Venkateshr	1	1880	Sep 8^th, 2006, 12:55am By: jbdavid
How to run simulation of verilogA files?	ADDA	3	950	Sep 5^th, 2006, 6:20am By: Geoffrey_Coram
Printing frequency in AC output « Pages 1 2 »	Marq Kole	21	339	Sep 1^st, 2006, 11:25pm By: jbdavid
Compiler Error of Verilog-A in Cadence-$dist_norm	littlekoala	3	102	Aug 30^th, 2006, 11:13pm By: Ken Kundert
phase-domain model of PLL in VerilogA	semitao	8	1614	Aug 30^th, 2006, 11:22am By: Ken Kundert
Post-processing capabilities in Verilog-AMS/Spectr	Faisal	3	3341	Aug 29^th, 2006, 11:36am By: jbdavid
How to creat a loop filter model in VerilogA	semitao	2	77	Aug 29^th, 2006, 11:25am By: jbdavid
Convergence with voltage parabola	mady79	2	2525	Aug 18^th, 2006, 1:31am By: mady79
Harder to converge in Monte Carlo sims???	PaulFerg	5	4699	Aug 17^th, 2006, 11:50pm By: Ken Kundert
How to creat a VCO model with jitter in VerilogA	semitao	7	1495	Aug 16^th, 2006, 12:34am By: semitao
Verilog-Ams Tutorial / Books	smily (Guest)	3	9518	Aug 5^th, 2006, 3:16am By: jbdavid
Using variables in structural elements.	Eugene	3	2966	Aug 3^rd, 2006, 6:38am By: jbdavid
How to model a divider with multiphase output?	wchlee	1	1698	Aug 3^rd, 2006, 6:29am By: jbdavid
syntax problem A <= #'B C;	MARCE (Guest)	2	2262	Aug 3^rd, 2006, 6:21am By: jbdavid
wreal in digital context	Monia (Guest)	1	1920	Aug 3^rd, 2006, 6:18am By: jbdavid
AMS Beginer: Need help w/ AMS netlisting from HED	Saroj Rout (Guest)	1	2119	Aug 3^rd, 2006, 6:03am By: jbdavid
Simple question about output assignment	Anexanhume	3	2999	Aug 3^rd, 2006, 5:53am By: jbdavid
Verilog-A vs Verilog AMS	Faisal	8	183	Aug 3^rd, 2006, 5:37am By: jbdavid

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