Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
one filter ok in SRF, hidden state when 2 cascaded	hawerchuk	0	1327	May 30^th, 2006, 3:45pm By: hawerchuk
problems with verilog-A generate	danmc	1	2953	May 16^th, 2006, 7:27am By: Geoffrey_Coram
PLI	MokoKoya	1	2098	May 15^th, 2006, 7:08am By: Andrew Beckett
how to model the non-volatile component?	circuitdesigner	0	1445	Apr 26^th, 2006, 2:28am By: circuitdesigner
Is there any Verilog-AMS course?	will3573	4	4677	Apr 22^nd, 2006, 12:17am By: Ken Kundert
Syntax error in case statement	yongjin CHOI	3	4187	Apr 21^st, 2006, 2:14am By: jbdavid
Performance/area tradeoff using several multiplier	rahulfloyd	1	2199	Apr 21^st, 2006, 2:10am By: jbdavid
Modeling high-z output in verilog-A	steve_mac	6	1559	Apr 21^st, 2006, 2:06am By: jbdavid
Verilog simulation: Can't descend into cell views	aprior	5	1753	Apr 21^st, 2006, 1:58am By: jbdavid
Op-Amp code and Ramp Input « Pages 1 2 »	Vikram Srinivasan (Guest)	16	23040	Apr 21^st, 2006, 1:43am By: jbdavid
Charge Pump with output voltage's limitation	jjun2003	7	8049	Apr 7^th, 2006, 6:33am By: Geoffrey_Coram
FBH-HBT Model	mahboul	7	1434	Apr 4^th, 2006, 8:15am By: Geoffrey_Coram
Verilog A Event	yaxazaa	2	3564	Mar 24^th, 2006, 2:18am By: Marq Kole
Multiple modules in verilog	ness9660	1	2672	Mar 22^nd, 2006, 9:06am By: Geoffrey_Coram
laplace_nd filter question	trond	2	3092	Mar 20^th, 2006, 4:11am By: Marq Kole
how to read and write in same file in verilogA	Badri	2	3131	Mar 20^th, 2006, 2:36am By: Marq Kole
dither model	trond	5	5724	Mar 17^th, 2006, 9:07am By: Ken Kundert
Problem on instantiating analog primitives in VAMS	sonis	6	5208	Mar 16^th, 2006, 1:51am By: sonis
A verilog novice...	ness9660	1	2674	Mar 6^th, 2006, 7:02pm By: Croaker
Frequency-to-current converter in phase domain « Pages 1 2 »	Emre	16	12919	Mar 6^th, 2006, 10:51am By: Ken Kundert

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