Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Fractional-N PLL Verilog-a Model	Cityblues	0	872	Nov 13^th, 2018, 5:17pm By: Cityblues
wreal net has multiple non-Z drivers	arupkg	1	1145	Oct 21^st, 2018, 4:49am By: Andrew Beckett
idtmod in wreal VAMS	deba	2	1484	Oct 1^st, 2018, 12:46am By: deba
Wire in Verilog A	Maverick_shastry	1	1135	Sep 26^th, 2018, 12:52pm By: Ken Kundert
Implement upper and lower current limits in op-amp model	elfmushroom	0	720	Sep 11^th, 2018, 7:26pm By: elfmushroom
high frequency source VS. long rise time(parallel RC) in transient simulation	Peng_Li	3	1594	Aug 26^th, 2018, 7:45pm By: Peng_Li
writing into a file	Horror Vacui	1	1187	Jul 23^rd, 2018, 8:52am By: Andrew Beckett
ideal switch convergence problem	liletian	5	2255	Jul 19^th, 2018, 10:18pm By: Ken Kundert
SKILL functions in VerilogA possible?	Horror Vacui	6	2795	Jun 20^th, 2018, 2:07am By: Horror Vacui
DC/Dc step up converter	ouijdane	0	867	Jun 13^th, 2018, 6:09am By: ouijdane
Hierarchical net reference question	SteveRosenbaum	3	1652	Jun 6^th, 2018, 2:25pm By: SteveRosenbaum
VerilogA - Pulse generator with reset	Jacob E. F. Overgaard	5	1247	May 5^th, 2018, 1:52pm By: Jacob E. F. Overgaard
How to jump from a forever cycling loop in Veriloga.	Jacki	1	1723	Feb 6^th, 2018, 8:57am By: Geoffrey_Coram
Netlisting failed with multiple Verilog-A blocks	yong_rfic	3	3861	Jan 31^st, 2018, 2:50pm By: andrew terry
Model Zero order hold in VerilogA	braid	1	1522	Jan 16^th, 2018, 4:34am By: cheap_salary
Is there a way to implement this kind of RC model in veriloga?	ray0923	4	2320	Jan 10^th, 2018, 6:22am By: Geoffrey_Coram
synthesize verilog-a	vaibhav16119	1	1324	Jan 2^nd, 2018, 1:47am By: Andrew Beckett
help with array and loop in verilog-A	Shahriar	1	617	Dec 21^st, 2017, 11:34pm By: Andrew Beckett
verilog-a question	filipe	10	9733	Dec 11^th, 2017, 12:02pm By: Geoffrey_Coram
MOSFET LEVEL 3 verilogA model help! « Pages 1 2 »	liletian	18	3288	Nov 22^nd, 2017, 7:44am By: Geoffrey_Coram

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