Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
2 way switch in verilog ams	Yuan	1	936	Feb 7^th, 2019, 8:28am By: Geoffrey_Coram
Negative power for flicker_noise()	cheap_salary	8	3588	Jan 11^th, 2019, 5:11am By: cheap_salary
Variable resistor	Seario	10	8688	Dec 27^th, 2018, 12:16am By: Peng_Li
Fractional-N PLL Verilog-a Model	Cityblues	0	935	Nov 13^th, 2018, 5:17pm By: Cityblues
wreal net has multiple non-Z drivers	arupkg	1	1220	Oct 21^st, 2018, 4:49am By: Andrew Beckett
idtmod in wreal VAMS	deba	2	1573	Oct 1^st, 2018, 12:46am By: deba
Wire in Verilog A	Maverick_shastry	1	1204	Sep 26^th, 2018, 12:52pm By: Ken Kundert
Implement upper and lower current limits in op-amp model	elfmushroom	0	755	Sep 11^th, 2018, 7:26pm By: elfmushroom
high frequency source VS. long rise time(parallel RC) in transient simulation	Peng_Li	3	1699	Aug 26^th, 2018, 7:45pm By: Peng_Li
writing into a file	Horror Vacui	1	1260	Jul 23^rd, 2018, 8:52am By: Andrew Beckett
ideal switch convergence problem	liletian	5	2413	Jul 19^th, 2018, 10:18pm By: Ken Kundert
SKILL functions in VerilogA possible?	Horror Vacui	6	2977	Jun 20^th, 2018, 2:07am By: Horror Vacui
DC/Dc step up converter	ouijdane	0	923	Jun 13^th, 2018, 6:09am By: ouijdane
Hierarchical net reference question	SteveRosenbaum	3	1771	Jun 6^th, 2018, 2:25pm By: SteveRosenbaum
VerilogA - Pulse generator with reset	Jacob E. F. Overgaard	5	1453	May 5^th, 2018, 1:52pm By: Jacob E. F. Overgaard
How to jump from a forever cycling loop in Veriloga.	Jacki	1	1983	Feb 6^th, 2018, 8:57am By: Geoffrey_Coram
Netlisting failed with multiple Verilog-A blocks	yong_rfic	3	4002	Jan 31^st, 2018, 2:50pm By: andrew terry
Model Zero order hold in VerilogA	braid	1	1595	Jan 16^th, 2018, 4:34am By: cheap_salary
Is there a way to implement this kind of RC model in veriloga?	ray0923	4	2467	Jan 10^th, 2018, 6:22am By: Geoffrey_Coram
synthesize verilog-a	vaibhav16119	1	1405	Jan 2^nd, 2018, 1:47am By: Andrew Beckett

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