Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Ideal SH time interleaving	John Rankin	1	921	Aug 2^nd, 2017, 5:31am By: John Rankin
Moved: hAMSter Model Editor Error Messages - Started by: loumbut5 This Topic has been moved to VHDL-AMS by Ken Kundert
Noise simulation using Verilog-A	giuls	9	6076	Jun 22^nd, 2017, 7:21am By: Geoffrey_Coram
Phase noise simulation using a verilog A model	iVenky	2	1466	Jun 17^th, 2017, 10:09pm By: Ken Kundert
AFS COSIM	subtr	0	887	Jun 16^th, 2017, 7:37am By: subtr
Reading a file in verilog	ouij	0	626	Jun 13^th, 2017, 6:53am By: ouij
Issue modeling sampler in RNM	Joe Shakya	13	3868	Jun 6^th, 2017, 11:38am By: Andrew Beckett
Regarding issue with absdelta	AMS_ei	4	2009	May 30^th, 2017, 12:08am By: Ken Kundert
Hidden state problem: selective switching off and on at minimum of a sinewave	Mauro	2	1375	May 24^th, 2017, 6:01am By: Mauro
Op-amp Macro Model in ahdlLib	hchanda	14	18898	May 22^nd, 2017, 7:59am By: Geoffrey_Coram
Resources usage	Abdullah	0	612	May 15^th, 2017, 3:29pm By: Abdullah
Veriloga module for current mode passive mixer	chethan_RFIC	2	1420	May 2^nd, 2017, 2:46am By: chethan_RFIC
@(cross statement triggering on constant value at sim start time	va_user	3	1762	Apr 20^th, 2017, 12:22am By: Ken Kundert
current measurement through $cds_iprobe	AMS_ei	4	3024	Apr 18^th, 2017, 8:44am By: AMS_ei
Accessing Global Variables in verilogA	subtr	1	1305	Apr 16^th, 2017, 12:09am By: Andrew Beckett
Custom Bit sequence in verilog-ams	bit_an	1	951	Apr 10^th, 2017, 8:07pm By: Ken Kundert
Modelling DAC non linearity using look up table	subtr	4	1425	Apr 6^th, 2017, 1:37pm By: Andrew Beckett
VerilogA code for Ideal MOS switch	ashrafSazid	1	1893	Apr 5^th, 2017, 12:10am By: Ken Kundert
Loop filter Verilog AMS	JeromeONeill	9	4267	Mar 24^th, 2017, 11:59pm By: Ken Kundert
Transient Effect	MMI	5	3471	Mar 15^th, 2017, 9:55am By: Geoffrey_Coram

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