Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
ncelab error	Dipankar	1	4612	Aug 12^th, 2009, 10:38am By: Riad KACED
AMS Simulator ConnectLib problem	Deb	2	229	Aug 12^th, 2009, 10:03am By: Riad KACED
Efficient way of Defining MACROs(Directives) Globally	Dipankar	2	142	Jul 11^th, 2009, 1:19am By: Dipankar
connect modules mystery in Cadence ams designer (OSS flow)	Dan Clement	11	12442	Jun 22^nd, 2009, 11:54am By: Dan Clement
AMS-Spectre PLL Simulation Problem	rajat	0	79	May 31^st, 2009, 8:03pm By: rajat
Moved: SOI Convergence Problems - Started by: emad This Topic has been moved to Circuit Simulators by Forum Administrator
spectreVerilog netlist problem	jsun	2	150	May 11^th, 2009, 4:30pm By: jsun
AMS sims with digital modules	ams_man	3	196	May 8^th, 2009, 9:13pm By: makelo
Analog block in AMS simulation	jefkat	1	123	May 6^th, 2009, 12:04am By: Paul Floyd
view in cadence mixed signal simulation	depend135	3	5884	May 4^th, 2009, 4:19pm By: makelo
mixed signal simulation problem	jsun	2	196	May 1^st, 2009, 3:25pm By: jsun
mixed mode sim with spectre verilog	jefkat	2	7132	May 1^st, 2009, 1:50pm By: jsun
Importing Verilog files in Virtuoso	jefkat	0	2378	Apr 30^th, 2009, 2:14am By: jefkat
ams simulation flow for pvt	lily	1	1966	Apr 24^th, 2009, 6:43am By: Andrew Beckett
simulating using Mentor-tools	Prateek	2	165	Apr 22^nd, 2009, 10:48pm By: Prateek
Power connection for verilog modules	R. Zakai	1	2194	Apr 15^th, 2009, 7:01am By: boe
what is the OSS/irun flow in AMS in ADE	idriss	1	2567	Apr 15^th, 2009, 3:06am By: Andrew Beckett
netlisting in ade with ams	idriss	2	3246	Apr 12^th, 2009, 9:49am By: Andrew Beckett
Spice sub-circuit in AMS simulation	R. Zakai	1	2205	Apr 4^th, 2009, 2:37pm By: Andrew Beckett
issue with elaborating in ams using ade	idriss	4	6146	Apr 1^st, 2009, 9:33am By: boe

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