Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
resrtiction on analog derivative operator	Aigneryu	3	4160	Dec 12^th, 2006, 5:56am By: Geoffrey_Coram
Modeling a controlled switch for currents	topquark	2	7237	Dec 8^th, 2006, 10:59pm By: jbdavid
How to replace "wait" statement in synthesis ?!?	AdamPod	1	2394	Dec 8^th, 2006, 10:36pm By: jbdavid
string parameter??	Aigneryu	2	3037	Dec 6^th, 2006, 6:26pm By: Aigneryu
DLL in verilog A	venka_arun	0	12523	Nov 24^th, 2006, 9:10pm By: venka_arun
Simulating ESD discharge in Verilog	Dimitri	2	3144	Nov 16^th, 2006, 11:34am By: Geoffrey_Coram
"Charge" and �"Flux" natures - theirs usefuln	Pavel	5	5086	Nov 16^th, 2006, 11:33am By: Geoffrey_Coram
A question about PLL behavior simulation.	Terry	1	3225	Nov 15^th, 2006, 6:41pm By: Terry
Behavioural model of DLL	venka_arun	0	2089	Nov 15^th, 2006, 5:45pm By: venka_arun
simulating behavioral lna gives wrong results	Jochen	11	11840	Nov 13^th, 2006, 8:16am By: Frank Wiedmann
Cadence Sample Library - cell names??	Pavel	12	2506	Nov 6^th, 2006, 12:32pm By: Geoffrey_Coram
how to start "Modelwriter"?	bk_mensch	2	143	Nov 2^nd, 2006, 7:43pm By: lrc
Statistical Analysis in Spectre	SATurn	2	3107	Oct 26^th, 2006, 1:13pm By: SATurn
Verilog-A: the meaning of gnd node?	Pavel	5	6881	Oct 23^rd, 2006, 5:01am By: Geoffrey_Coram
how to simulate verilogA models	chviswanadh	8	9382	Oct 15^th, 2006, 3:38am By: chviswanadh
modeling CMFB in opamp models	jbdavid	0	2226	Oct 13^th, 2006, 2:08pm By: jbdavid
Problem with pole setting in verilogA	chviswanadh	1	98	Oct 12^th, 2006, 4:30am By: Geoffrey_Coram
How to model settling time of OTA	chviswanadh	0	346	Oct 10^th, 2006, 5:51am By: chviswanadh
How to model an envelope detector in verilog-a?	danda821	1	4923	Oct 6^th, 2006, 3:34am By: ACWWong
a basic verilogA question	lrc	3	1019	Oct 2^nd, 2006, 7:03am By: lrc

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