Testing a High Speed Differential TIA

outputs of lvcmos buffer togather

SSN setup

Generating MATLAB Bathtub Curves from Cadence Spectre Eye Diagrams

Moved: Custom Bit sequence in verilog-ams - Started by: bit_an
This Topic has been moved to Verilog-AMS by Ken Kundert

Architectures of CDR in the SerDes IC

Oversampling clock and data recovery for SerDes communication

How to connect PCB and FPGA board?

loop unroll H1 timing

3.3 v decap using 1.8 volt tolerant mos decaps without using MOM

Do we have termination for optical interconnects?

Checking for stability in a bang bang CDR

pre and post cursor information from S21

Partial response DFE vs. Loop Unrolling DFE (look ahead dfe)

Regarding Serial Link standrds

Linearizing a Bang-Bang (or Alexander) Phase Detector

Active inductor for high speed operation (> 12GHz) in 16nm finfet process

CML buffer Band width extension techniques

LVDS driver

Precursor ISI cancellation