Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Delay Locked Loop Design	saurabh3488	1	3074	Mar 12^th, 2015, 11:08am By: Jeffrey987
Jitter amplification	raja.cedt	3	1225	Dec 3^rd, 2014, 11:54am By: loose-electron
Weak pull up/down and keeper in IOs	dewy	1	5354	Aug 12^th, 2014, 11:48am By: loose-electron
DDR/IO standards	sini	2	4102	Jul 30^th, 2014, 11:41pm By: dewy
pll chargepump one to one correspondence between static phase error and ref spur	yvkrishna	0	2066	Mar 27^th, 2014, 3:05pm By: yvkrishna
Self bias PLL	raja.cedt	1	7119	Feb 23^rd, 2014, 9:10pm By: carlgrace
What do you mean by "synchronous edge detection"?	iVenky	1	3320	Feb 23^rd, 2014, 2:43pm By: BackerShu
Snr Required for PAM4 receiver	raja.cedt	0	2675	Dec 18^th, 2013, 6:32am By: raja.cedt
Noise isolation using back to back diodes across different power domains	petitivoire	2	550	Nov 29^th, 2013, 8:50am By: petitivoire
ISI is caused by cable's group delay distortion and amp attenuation	andyseu	0	6104	Oct 8^th, 2013, 1:31am By: andyseu
group delay of a backplane channel	ywguo	5	6809	Sep 28^th, 2013, 6:23pm By: andyseu
BER measurement	raja.cedt	4	5309	Aug 14^th, 2013, 6:30pm By: Ken Kundert
Delay Locked Loop Design	saurabh3488	2	4027	Jul 22^nd, 2013, 9:24am By: tm123
Eye-Diagram	raja.cedt	3	5750	Jun 8^th, 2013, 3:22am By: ywguo
low BW pll loop filter	raja.cedt	4	5587	Apr 17^th, 2013, 2:23pm By: smlogan
base line wanderwall consideration	raja.cedt	7	7785	Mar 25^th, 2013, 6:51pm By: colossus_bade
impact of group delay on eye closser	raja.cedt	1	3147	Mar 1^st, 2013, 11:18pm By: ywguo
How to implement large delay?	BackerShu	8	10847	Feb 25^th, 2013, 2:31pm By: loose-electron
High Speed Serializer Architecture	analog_design	3	981	Jan 16^th, 2013, 8:41pm By: loose-electron
Transition density estimation	BackerShu	7	7701	Dec 29^th, 2012, 5:52pm By: BackerShu

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