Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Hogge PD up/dn pulses are skewed	neoflash	0	428	Jun 1^st, 2023, 10:50pm By: neoflash
anyone is using python to do serdes analysis?	neoflash	1	625	Mar 16^th, 2023, 1:25pm By: dnw
learning SERDES	AnalogDE	1	1287	Apr 27^th, 2022, 7:18pm By: synsilvers
How to plot eye for loop unrolled DFE	neoflash	0	414	Mar 18^th, 2022, 10:55am By: neoflash
Moved: Error in Unary negation operator in VerilogA designing charge pump - Started by: kankanas This Topic has been moved to Verilog-AMS by Ken Kundert
Package substrate layer definition 7-n-7	neoflash	0	388	Dec 31^st, 2021, 11:48pm By: neoflash
VGA and CTLE for 112G-XSR	rajeee1000	0	622	Aug 10^th, 2021, 7:58am By: rajeee1000
Phase interpolator- Voltage vs Current mode	iVenky	0	566	Jun 28^th, 2021, 4:45pm By: iVenky
Why SPI chip select signal is active low?	neoflash	1	1319	Jan 8^th, 2020, 7:39am By: Frank Wiedmann
BER measurement of CDR using Cadence	kazkou	1	1603	Nov 29^th, 2019, 12:48am By: sheldon
Why do ring oscillators have poor Quality factor?	Venky_analog	5	2382	Feb 3^rd, 2019, 12:44pm By: iVenky
jitter tolerance analysis in cadence	kazkou	2	1955	Jan 26^th, 2019, 7:48pm By: kazkou
How to simulate Differential return loss SDD, and Common mode return loss SCC	darkhorse	0	1486	Aug 12^th, 2018, 9:31pm By: darkhorse
Quantifying Eye Diagram for high-speed SERDES channel	aguntuk	1	2353	Apr 17^th, 2018, 2:46pm By: repah
State-of-the-art speed for high-speed electrical channel	aguntuk	1	2173	Apr 17^th, 2018, 2:44pm By: repah
relation between CMOS technology and speed of I/O	aguntuk	2	112	Apr 17^th, 2018, 2:41pm By: repah
Moved: S-ParameterSimulation using T-Line in ADS - Started by: aguntuk This Topic has been moved to Circuit Simulators by Ken Kundert
Self inductance Versus Loop Inductance of a trace	curious	2	2250	Dec 10^th, 2017, 7:08pm By: curious
Why HBM model uses 1.5K resistor to model human body resistance?	neoflash	1	2174	Nov 16^th, 2017, 4:24pm By: Maks
Moved: Looking for Verilog - A Code for 2^31-1 PBRS Generator - Started by: repah This Topic has been moved to Verilog-AMS by Ken Kundert

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