Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Setting up VersionSync for small group	Kudie	3	4452	Jan 5^th, 2010, 2:26am By: Andrew Beckett
how to use encounter to place digital cell and analog abstract cell?	jsun	0	2109	Oct 30^th, 2009, 5:43pm By: jsun
class E power amplifier design with 0.18um tsmc designkit in ADS	roberto11	0	3242	Oct 1^st, 2009, 2:46am By: roberto11
LOCKING PROBLEM IN CADENCE	VINAY RAO	2	3499	Sep 10^th, 2009, 12:05am By: ywguo
Problems assigning parameterizable values in cell (Cadence ADE)	vivkr	6	8778	Sep 8^th, 2009, 3:08am By: Frank Wiedmann
Get Layout Objects in hierarchical view with skill	Berti	1	3185	Aug 15^th, 2009, 6:59am By: Andrew Beckett
Capturing wave forms from ocean/skill	gzatorre	1	4099	Aug 15^th, 2009, 6:52am By: Andrew Beckett
Synopsys Design Compiler: Mismatch between logical/physical library.	pgbackup	0	4709	Jul 19^th, 2009, 7:11pm By: pgbackup
Creating new symbol view for d_ff cell	santo	2	869	Jul 13^th, 2009, 8:42am By: santo
Schematic as stop view in icfb	Haydar	1	4051	Jul 10^th, 2009, 8:40am By: Andrew Beckett
AA/Spectre probing devices in included subcircuits	Haydar	2	3624	Jul 10^th, 2009, 8:39am By: Andrew Beckett
Deleting CDF Parameters by using SKILL script	analogue_guy	1	4004	Jun 30^th, 2009, 4:47pm By: Haydar
Problems with simulating using technology library in ic5141	andrew_wee	1	2651	May 12^th, 2009, 8:53pm By: pancho_hideboo
Importing Verilog using Verilog In	jefkat	0	1847	Apr 29^th, 2009, 8:52am By: jefkat
About the Standard Cell application in P&R	gaom9	1	3840	Apr 24^th, 2009, 6:55am By: Andrew Beckett
Hierarchical Copy	ic_engr	2	1026	Apr 22^nd, 2009, 8:31am By: ic_engr
CDL import	salty	0	2073	Apr 17^th, 2009, 7:56am By: salty
'Check and Save' all cells in Cadence	Paul Geraedts	2	8306	Apr 16^th, 2009, 9:18am By: bernd
Passing monte carlo parameters to verilog-a module.	cgt	2	4729	Apr 6^th, 2009, 7:36pm By: jbdavid
In Composer, pass down parameters for veriloga block	neoflash	1	2729	Apr 4^th, 2009, 2:45pm By: Andrew Beckett

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