Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
veriloga -> loop of rigid branches (shorts)	marben	4	9201	Dec 1^st, 2005, 3:55am By: Geoffrey_Coram
The methods to avoid the negative delay time	tumeda	0	1610	Nov 17^th, 2005, 1:40am By: tumeda
Analog bus limitation, any work-around ?	ekne	4	3753	Nov 15^th, 2005, 7:31pm By: ekne
Diode modeling probelm	sonis	5	1271	Nov 9^th, 2005, 9:48am By: jbdavid
delay function in Verilog-A	RobertZ	2	3991	Nov 4^th, 2005, 9:28am By: RobertZ
how to pass a string in Verilog-A	RobertZ	8	25329	Nov 4^th, 2005, 4:55am By: Andrew Beckett
Verilog help	engineer21	0	2017	Oct 23^rd, 2005, 7:21pm By: engineer21
mixing behavioral and device level models	Eugene	6	5985	Oct 21^st, 2005, 7:48pm By: Eugene
2 phase clock generator w/o hidden state?	huber	12	14245	Oct 18^th, 2005, 10:53pm By: rf-design
Test for the divider Mode without Hiddenstate	tumeda	1	2292	Oct 18^th, 2005, 9:50am By: Ken Kundert
variloga keyword for frequency?	manyoki	6	6064	Oct 17^th, 2005, 9:55am By: Jess Chen
Write to file	noreng	10	13553	Oct 17^th, 2005, 1:25am By: jbdavid
Aborting a simulation thru VerilogA	Eugene	9	347	Oct 14^th, 2005, 2:39pm By: manyoki
Is this possible !!!	jefkat	6	253	Oct 12^th, 2005, 2:39am By: jefkat
VIM syntax highlighting for Verilog-AMS 2.2	Myles Prather	5	1505	Oct 12^th, 2005, 1:41am By: jbdavid
phase noise - jitter relationship « Pages 1 2 »	trond	16	3238	Oct 9^th, 2005, 11:41pm By: trond
synthesizable non-integer delays	Paul Geraedts	1	2534	Oct 4^th, 2005, 5:55pm By: jbdavid
Cross-domain access in VerilogAMS	chakrabartis	1	2366	Oct 4^th, 2005, 5:49pm By: jbdavid
Simple questions from a starter	moisiad	9	9197	Oct 4^th, 2005, 5:21pm By: jbdavid
Error message from divider model without HiddenSta	tumeda	1	2215	Oct 2^nd, 2005, 12:38am By: Andrew Beckett

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