Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
how to model a gated voltage controlled oscillator	beabroad1	0	1640	Jun 24^th, 2005, 4:27pm By: beabroad1
parsing of ahdl failed - cadence model writer	trond	2	3362	Jun 8^th, 2005, 7:19am By: trond
Array size function in Verilog-A/AMS?	mmirmak	1	2794	Jun 6^th, 2005, 8:53am By: Geoffrey_Coram
Noise table using CASE statement	Nathan (Guest)	6	5470	Jun 6^th, 2005, 8:10am By: Geoffrey_Coram
problems with compiler directives	Andrew Burton (Guest)	5	4669	Jun 6^th, 2005, 6:31am By: Geoffrey_Coram
PSS convergence of a VCO with a divider	tromeros	1	3013	May 31^st, 2005, 10:46am By: Andrew Beckett
Does the Netlist include the Verilog-A?	kamesh419	1	2437	May 25^th, 2005, 10:09pm By: Andrew Beckett
Hidden state in VCO	tromeros	1	2408	May 23^rd, 2005, 10:43pm By: Ken Kundert
Multi-tone voltage source in PSS simulation	wchlee	2	3049	May 17^th, 2005, 10:17am By: Andrew Beckett
VCO in Verilog-A/MS question	trond	5	104	May 4^th, 2005, 4:33am By: trond
ncverilog simulation	senthil	1	2281	Apr 18^th, 2005, 4:46am By: Andrew Beckett
Standard Power supply	vikramts	3	3258	Apr 2^nd, 2005, 7:52am By: Andrew Beckett
Synthesis of HDL codes	vikramts	2	2705	Mar 30^th, 2005, 7:02am By: vikramts
Opamp with Positive Feedback	Vikram Srinivasan (Guest)	11	149	Mar 26^th, 2005, 10:16am By: vikramts
Standard Technology for MOS devices	vikramts	2	2886	Mar 21^st, 2005, 7:11am By: vikramts
VerilogAMS is perfect for spread spectrum sims	bortecene	0	1622	Mar 17^th, 2005, 11:01am By: bortecene
Gaussian Synapse Model Problem	Vikram Srinivasan (Guest)	1	2161	Mar 14^th, 2005, 8:07am By: vikramts
read data using $readmem	bricesg	2	3433	Mar 8^th, 2005, 1:24am By: Andrew Beckett
Cadence PLL library	gogomi	1	46	Mar 7^th, 2005, 8:53pm By: Eugene
Reading data from disk	dokim4	6	7149	Mar 7^th, 2005, 12:41pm By: mgehring

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