Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Verilog-In failed	Pavel	4	7307	Dec 28^th, 2006, 4:41am By: Pavel
Export layout from Encounter to Virtuoso	lrc	0	3010	Dec 10^th, 2006, 9:01pm By: lrc
Changing the text editors in Artist	Ken Kundert	7	20999	Oct 19^th, 2006, 6:03pm By: lrc
Can CDL netlist automatically be in upper case?	vibren	6	10283	Oct 19^th, 2006, 2:14am By: bernd
copying questions in Virtuoso layout tool	CDR	7	9401	Oct 18^th, 2006, 6:11pm By: graywang
CSV file from OCEAN	Tommy	2	5787	Sep 22^nd, 2006, 12:05am By: jbdavid
The flow of the PDK design?	taos	4	6148	Sep 12^th, 2006, 1:40pm By: Andrew Beckett
How to import a spice netlist to schematic	Tommy	4	2456	Aug 20^th, 2006, 3:57pm By: Andrew Beckett
LVS Parameters for Presistors, Sources, etc.	keplin	2	6720	Aug 7^th, 2006, 12:37am By: bernd
Instantiating a netlist	August West	8	20557	Aug 4^th, 2006, 10:32pm By: sheldon
Aptivia / VSDE	asdf	2	5509	Aug 3^rd, 2006, 4:24am By: jbdavid
verilog A editor	RobertZ	2	5628	Aug 3^rd, 2006, 4:09am By: jbdavid
DFII->DM library conversion	ywguo	2	4105	Aug 3^rd, 2006, 4:01am By: jbdavid
cdl out problem	jcpu2006	3	921	Aug 3^rd, 2006, 3:35am By: jbdavid
problem with variable	asdf	2	6112	Aug 3^rd, 2006, 3:23am By: jbdavid
About symbol draw	taos	4	6860	Jul 28^th, 2006, 5:34am By: bernd
how to solve this LVS error?	jaylin79	1	3321	Jul 24^th, 2006, 2:02pm By: Andrew Beckett
Output in ASCII format	aamar	1	3971	Jul 24^th, 2006, 2:00pm By: Andrew Beckett
compilation problem with behavioral elements ?	TT	1	3166	Jul 13^th, 2006, 5:19pm By: TT
Problems to start LVS in assura3.1.4	cyrus	2	4018	Mar 2^nd, 2006, 8:58am By: cyrus

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