Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
How do I prepare a hard IP?	ywguo	1	3165	Aug 16^th, 2004, 1:11am By: ywguo
Comparison of two layouts for resistor	ywguo	2	4375	Aug 1^st, 2004, 12:18pm By: Shiva (Guest)
What is 5V tolerant?	ywguo	1	3503	Jul 30^th, 2004, 2:52pm By: Nader (Guest)
"generate" Statement	Nader (Guest)	2	8019	Jul 30^th, 2004, 11:48am By: Nader (Guest)
Layout issue of MIM caps	ywguo	5	1217	Jul 1^st, 2004, 12:32am By: Paul
Should nwell shield be tied to vdd or gnd?	ywguo	2	5116	Jun 27^th, 2004, 9:39pm By: ywguo
How does PDRACULA select substrate connection?	Yawei Guo (Guest)	2	4392	Jun 7^th, 2004, 11:14pm By: ywguo
prescaler design	sudhacr	0	338	May 15^th, 2004, 3:25am By: sudhacr
digital library for mixed-signal	ravi	5	2240	May 13^th, 2004, 10:52am By: Andrew Beckett
Offset PLL stuffs!	zinmel	2	1413	May 5^th, 2004, 11:55pm By: Frank Wiedmann
Any reference for voltage reference buffer?	ywguo	0	2574	May 5^th, 2004, 3:59am By: ywguo
ADC simulation with SpectreRF	Stephan Weber (Guest)	0	2721	Apr 30^th, 2004, 12:09am By: Stephan Weber (Guest)
CMOS Switches in SC sigma-delta modulator	boa	3	6150	Apr 26^th, 2004, 9:24am By: boa
Any refrerence on 12-bit 40 MHz ADC in 0.35 micron	Faisal Mateen (Guest)	1	3662	Apr 26^th, 2004, 8:42am By: boa
measures for substrate noise reduction	ywguo	0	2790	Apr 11^th, 2004, 7:51am By: ywguo
opamp'problem in the sc network	alice_alice_nc	2	4649	Apr 8^th, 2004, 12:57am By: alice_alice_nc
Re: about sc filter simulation	Ken Kundert	3	6267	Mar 24^th, 2004, 7:35am By: Ken Kundert
help!	jeffyan	0	3004	Mar 23^rd, 2004, 6:57am By: jeffyan
How can i test pipelinedADC	potter	0	2783	Mar 20^th, 2004, 8:52pm By: potter
Is timing important for pipelined ADC?	potter	0	2771	Mar 18^th, 2004, 10:09am By: potter

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