Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
generating schematics from (cdl/verilog/etc?)	analog2000	1	13796	May 8^th, 2008, 4:54am By: ywguo
how to change schematic automatically	Julian18	2	4810	May 3^rd, 2008, 1:44pm By: haikom
Virtuoso schematic editor Trouble	pancho_hideboo	0	2465	Apr 8^th, 2008, 12:12am By: pancho_hideboo
How to keep designers and reusers up-to-date	svenn	2	4681	Mar 4^th, 2008, 3:33am By: rf-design
TT	TT	4	9453	Dec 25^th, 2007, 4:26am By: rajdeep
CDF parameters are not recogniszed by verilog cell	rajdeep	1	3928	Dec 24^th, 2007, 4:31am By: rajdeep
Entering paramter through symbol interface	rajdeep	1	2931	Dec 18^th, 2007, 8:32pm By: rajdeep
Any Laker users here?	joel	2	9678	Sep 26^th, 2007, 2:18pm By: joel
how to write sequential program using SKILL	rajdeep	2	3771	Sep 17^th, 2007, 12:43pm By: haikom
Accessing signal values during simulation	rajdeep	4	5122	Aug 18^th, 2007, 4:16pm By: sheldon
Problem in accessing hierarchy with OCEAN	subho	1	2719	Aug 16^th, 2007, 4:35am By: haikom
what do i need for auto-routing of analog circuit	dpx4086	3	4389	Aug 16^th, 2007, 4:30am By: haikom
Moved: Resuming transient simulation in Spectre - Started by: Forum Administrator This Topic has been moved to Circuit Simulators by Forum Administrator.
design database synchronization	Pavel	1	2834	Jul 31^st, 2007, 6:12am By: Bill Toole
Need program to extract schematics from a netlist	Unique	2	3910	Jul 29^th, 2007, 11:15pm By: Unique
Extract spectre netlist issue	trashbox	5	1987	Jun 27^th, 2007, 1:39pm By: Ken Kundert
Synthesis of CML circuits	krishnap	1	2929	Jun 21^st, 2007, 12:24pm By: svenn
cells summary in schematic	Cri Azzolini	1	2949	Jun 21^st, 2007, 2:41am By: ACWWong
Cadence hangs when dismissing properties dialog	stephen	0	2016	Jun 15^th, 2007, 12:33pm By: stephen
Alternate CAD tools for Analog/Custom IC Design	SRF Tech	5	6726	Jun 4^th, 2007, 11:09am By: mg777

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