Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
generating schematics from (cdl/verilog/etc?)	analog2000	1	14241	May 8^th, 2008, 3:54am By: ywguo
how to change schematic automatically	Julian18	2	5396	May 3^rd, 2008, 12:44pm By: haikom
Virtuoso schematic editor Trouble	pancho_hideboo	0	2702	Apr 7^th, 2008, 11:12pm By: pancho_hideboo
How to keep designers and reusers up-to-date	svenn	2	5203	Mar 4^th, 2008, 3:33am By: rf-design
TT	TT	4	10068	Dec 25^th, 2007, 4:26am By: rajdeep
CDF parameters are not recogniszed by verilog cell	rajdeep	1	4207	Dec 24^th, 2007, 4:31am By: rajdeep
Entering paramter through symbol interface	rajdeep	1	3233	Dec 18^th, 2007, 8:32pm By: rajdeep
Any Laker users here?	joel	2	10103	Sep 26^th, 2007, 1:18pm By: joel
how to write sequential program using SKILL	rajdeep	2	4123	Sep 17^th, 2007, 11:43am By: haikom
Accessing signal values during simulation	rajdeep	4	5641	Aug 18^th, 2007, 3:16pm By: sheldon
Problem in accessing hierarchy with OCEAN	subho	1	2991	Aug 16^th, 2007, 3:35am By: haikom
what do i need for auto-routing of analog circuit	dpx4086	3	4933	Aug 16^th, 2007, 3:30am By: haikom
Moved: Resuming transient simulation in Spectre - Started by: Forum Administrator This Topic has been moved to Circuit Simulators by Forum Administrator.
design database synchronization	Pavel	1	3189	Jul 31^st, 2007, 5:12am By: Bill Toole
Need program to extract schematics from a netlist	Unique	2	4340	Jul 29^th, 2007, 10:15pm By: Unique
Extract spectre netlist issue	trashbox	5	2642	Jun 27^th, 2007, 12:39pm By: Ken Kundert
Synthesis of CML circuits	krishnap	1	3225	Jun 21^st, 2007, 11:24am By: svenn
cells summary in schematic	Cri Azzolini	1	3256	Jun 21^st, 2007, 1:41am By: ACWWong
Cadence hangs when dismissing properties dialog	stephen	0	2205	Jun 15^th, 2007, 11:33am By: stephen
Alternate CAD tools for Analog/Custom IC Design	SRF Tech	5	7333	Jun 4^th, 2007, 10:09am By: mg777

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