Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
How to speed up simulation run time with VerilogA?	Idan Kligvasser	2	3617	Dec 27^th, 2012, 4:56am By: Idan Kligvasser
Bind to schematic and verilog view for standard cells	ywguo	0	109	Nov 30^th, 2012, 1:56am By: ywguo
Does AMS support bsimsoi4.3 model	jeffrey-peng	1	3986	Jul 20^th, 2012, 11:52am By: Geoffrey_Coram
How does the analog solver deal with multi-discipline AMS Models	jerome_ams	0	1953	Jun 26^th, 2012, 8:45am By: jerome_ams
What is your choice of simulator for MS system of all-corners?	nieh	1	3892	Jun 13^th, 2012, 4:24am By: nieh
Dout looks HiZ for E2L_2_inhconn	ywguo	6	8454	May 23^rd, 2012, 11:20am By: rsmithuf
AMS simulation results	mtp3	10	10652	May 16^th, 2012, 10:59am By: mtp3
Standard Cell Libraries in AMS	mtp3	1	3375	May 16^th, 2012, 1:43am By: ywguo
Virtuoso AMS: ERROR	analogue_guy	4	8401	May 9^th, 2012, 10:26am By: Geoffrey_Coram
Problem simulating with AMS Simvision	mtp3	8	8712	May 9^th, 2012, 3:23am By: mtp3
ADE XL create local variable from verilog ams code...	nzborsti	8	2290	Apr 26^th, 2012, 12:28am By: nzborsti
Initial conditions Ring Oscilator - spectre simulator	Polux	5	6375	Apr 16^th, 2012, 4:28am By: Polux
Virtuoso AMS: test fixture flag	analogue_guy	0	2227	Apr 5^th, 2012, 1:58am By: analogue_guy
Which one dominates, timescale in irunArgs or std cell module?	ywguo	1	3157	Apr 2^nd, 2012, 11:43am By: boe
detailed resolution must be used with inherited connection. Why?	ywguo	1	2503	Apr 2^nd, 2012, 11:38am By: boe
Moved: ADS convergence problems - Started by: Polux This Topic has been moved to Circuit Simulators by Forum Administrator
ICCAP	Polux	0	1626	Mar 28^th, 2012, 4:58am By: Polux
ICCAP input setup using variable	Polux	0	1846	Mar 20^th, 2012, 3:31am By: Polux
Virtuoso AMS : Values not seen in Waveforms	deepak srinivasan	13	3360	Mar 6^th, 2012, 7:26am By: boe
SpectreVerilog: "reset" signal stays in "stx"	ahhfyz	1	2527	Feb 27^th, 2012, 6:37am By: boe

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