Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
ncelab DLWTLK error	nivani	1	2472	May 13^th, 2016, 10:10am By: Geoffrey_Coram
Simulation of Digital class D amplifier using Cadence AMS simulation	ananya	0	1559	May 2^nd, 2016, 11:31am By: ananya
HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?	binod23	1	2148	Apr 21^st, 2016, 12:51pm By: Geoffrey_Coram
need help:ncvlog error	pk9617	2	3531	Nov 23^rd, 2015, 7:06am By: Joeyao Chou
Run oss+irun Elaboration error	petitidiot	0	1903	Sep 28^th, 2015, 8:26am By: petitidiot
how to write .do file for batch simulation in ADVance MS	Harry_108	1	3146	Jun 24^th, 2015, 2:35am By: Harry_108
� (NP+S) divider not working	cktdesigner	11	249	Apr 13^th, 2015, 10:34am By: Geoffrey_Coram
How to save digital signal in mixed-signal simulating using spectreVerilog	wendyyang100	4	6695	Mar 30^th, 2015, 12:00pm By: Ken Kundert
MONTE CARLO ANALYSIS IN CADENCE	Mir	2	965	Mar 26^th, 2015, 9:52am By: Mir
$bound_step not working	cktdesigner	9	9052	Mar 16^th, 2015, 7:26am By: cktdesigner
Multiple Supply in a chip	Aj1234	1	668	Oct 13^th, 2014, 3:44am By: boe
how to create config view and simulate verilog-AMS code	susona	6	135	May 7^th, 2014, 8:16am By: boe
Open source tools for AMS simulation	rogerio	1	2757	Apr 16^th, 2014, 10:45am By: Geoffrey_Coram
Does spectreVerilog only support Verilog module with clk under 1GHz?	Lynn Lou	2	4236	Oct 8^th, 2013, 5:59am By: Lynn Lou
how to apply .vcd(.trn) stimulus to cadence schematic?	visbi	4	8866	Aug 13^th, 2013, 9:09pm By: sheldon
Corners	melinda	0	3280	May 30^th, 2013, 5:58am By: melinda
digital output keeps 0 in spectreverilog simulation	ahhfyz	1	3055	May 14^th, 2013, 6:38am By: boe
Analog simulation timescale is off from actual simulation time	AllanDK	0	3255	Mar 20^th, 2013, 3:04am By: AllanDK
Errors in AMS simulation	busoni	0	2902	Mar 8^th, 2013, 1:07am By: busoni
Blowing up of current in Cadence Spectre simulation	batmanbeginz	2	7878	Feb 26^th, 2013, 7:48am By: Geoffrey_Coram

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