Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
need help:ncvlog error	pk9617	2	2710	Nov 23^rd, 2015, 7:06am By: Joeyao Chou
Run oss+irun Elaboration error	petitidiot	0	1471	Sep 28^th, 2015, 8:26am By: petitidiot
how to write .do file for batch simulation in ADVance MS	Harry_108	1	2418	Jun 24^th, 2015, 2:35am By: Harry_108
� (NP+S) divider not working	cktdesigner	11	6512	Apr 13^th, 2015, 10:34am By: Geoffrey_Coram
How to save digital signal in mixed-signal simulating using spectreVerilog	wendyyang100	4	5092	Mar 30^th, 2015, 12:00pm By: Ken Kundert
MONTE CARLO ANALYSIS IN CADENCE	Mir	2	3881	Mar 26^th, 2015, 9:52am By: Mir
$bound_step not working	cktdesigner	9	6395	Mar 16^th, 2015, 7:26am By: cktdesigner
Multiple Supply in a chip	Aj1234	1	2650	Oct 13^th, 2014, 3:44am By: boe
how to create config view and simulate verilog-AMS code	susona	6	6303	May 7^th, 2014, 8:16am By: boe
Open source tools for AMS simulation	rogerio	1	2150	Apr 16^th, 2014, 10:45am By: Geoffrey_Coram
Does spectreVerilog only support Verilog module with clk under 1GHz?	Lynn Lou	2	3263	Oct 8^th, 2013, 5:59am By: Lynn Lou
how to apply .vcd(.trn) stimulus to cadence schematic?	visbi	4	7253	Aug 13^th, 2013, 9:09pm By: sheldon
Corners	melinda	0	2805	May 30^th, 2013, 5:58am By: melinda
digital output keeps 0 in spectreverilog simulation	ahhfyz	1	2305	May 14^th, 2013, 6:38am By: boe
Analog simulation timescale is off from actual simulation time	AllanDK	0	2702	Mar 20^th, 2013, 3:04am By: AllanDK
Errors in AMS simulation	busoni	0	2455	Mar 8^th, 2013, 1:07am By: busoni
Blowing up of current in Cadence Spectre simulation	batmanbeginz	2	6556	Feb 26^th, 2013, 7:48am By: Geoffrey_Coram
How to speed up simulation run time with VerilogA?	Idan Kligvasser	2	2692	Dec 27^th, 2012, 4:56am By: Idan Kligvasser
Bind to schematic and verilog view for standard cells	ywguo	0	2850	Nov 30^th, 2012, 1:56am By: ywguo
Does AMS support bsimsoi4.3 model	jeffrey-peng	1	3350	Jul 20^th, 2012, 11:52am By: Geoffrey_Coram

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