Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
the noise model of 0.6um CMOS	dandelion	0	1516	Oct 18^th, 2005, 6:42pm By: dandelion
Question on a VCO design with differential stage « Pages 1 2 »	tumeda	16	11674	Oct 17^th, 2005, 12:18am By: Paul
Sampled noise simulation w/ Spectre	chiu	2	2687	Oct 12^th, 2005, 3:51pm By: chiu
sar adc design	arsenal_he	2	2628	Oct 12^th, 2005, 11:47am By: arsenal_he
curvature on bandgap voltage reference	coffeecat	3	3018	Oct 9^th, 2005, 5:43am By: sheldon
Return Loss Measurement & Balun	giacomophx	4	7140	Oct 8^th, 2005, 11:59am By: giacomophx
Low temperature simulation of a simple NMOS	sphere83	4	3475	Oct 4^th, 2005, 7:40pm By: sphere83
Increase the quality factor of Sallen-key bandpass	Analoger	0	1279	Oct 3^rd, 2005, 1:47am By: Analoger
Application of on-chip bandgap	Analoger	7	5697	Sep 29^th, 2005, 7:24pm By: Analoger
Very Low Power Crystal Oscillator	ramakrishna	4	5852	Sep 29^th, 2005, 6:39am By: vivkr
Switched Cap. filter	atul	4	4179	Sep 25^th, 2005, 6:49pm By: Ken Kundert
design RISC processor using cadence tools	sri_1983	4	3550	Sep 25^th, 2005, 2:34pm By: Paul
question on ldo voltage regulator	navin_kumar	4	4037	Sep 25^th, 2005, 1:48am By: ywguo
PLL loop stability Fundamentals	simon1	5	7367	Sep 24^th, 2005, 12:35am By: vivkr
question on bandgap voltage reference	navin_kumar	1	1923	Sep 22^nd, 2005, 1:52pm By: golden apples (Guest)
connection between bandwidth and step response?	Croaker	6	143	Sep 21^st, 2005, 5:32pm By: wued
Sigma Delta ADC delay	ic_engr	3	4505	Sep 21^st, 2005, 9:02am By: sheldon
using transient analysis for stability checks « Pages 1 2 »	Croaker	17	16282	Sep 15^th, 2005, 2:48pm By: Croaker
How to reduce PLL jitter?	vijay	0	2858	Sep 15^th, 2005, 4:42am By: vijay
problems with convergence in PSS	ethan	0	1641	Sep 14^th, 2005, 10:08am By: ethan

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