Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
ESD strategy in a multi-power domains chip « Pages 1 2 »	LL	16	21934	Nov 13^th, 2006, 2:32pm By: SRF Tech
the PWD vs. the TTL input level &nb	dandelion	2	3847	Nov 8^th, 2006, 1:05am By: ywguo
Hysterisis characetristics for CMOS level output	dandelion	4	213	Oct 25^th, 2006, 7:40am By: SRF Tech
ESD circuit question?	email_gz	9	12692	Oct 22^nd, 2006, 10:50am By: chase.ng
latch up failure due to design ?	jason_class	2	3844	Oct 20^th, 2006, 11:55pm By: jason_class
how to calculate the output impedance of an CMOS o	phawk	1	4281	Oct 10^th, 2006, 7:44am By: SRF Tech
The nwell underneath the output pad	dandelion	1	2804	Sep 26^th, 2006, 3:21am By: ACWWong
Difference Between LVDS line Driver & CML drivers	schmitt	2	9055	Sep 23^rd, 2006, 11:59am By: jbdavid
Self biased inverter as receiver	chase.ng	3	6256	Sep 15^th, 2006, 12:40pm By: loose-electron
digital isolation using Pulse transformer	Lanzones	4	5232	Sep 8^th, 2006, 3:35am By: Lanzones
duty cycle requirement for the input of CDR	dandelion	4	5120	Sep 5^th, 2006, 11:38pm By: ywguo
high speed IO applications	steven	1	2975	Aug 29^th, 2006, 12:31pm By: jbdavid
The peak current and vias number	dandelion	2	781	Aug 21^st, 2006, 2:45pm By: ACWWong
A question on the PWD of output signal	dandelion	0	2015	Aug 17^th, 2006, 1:44am By: dandelion
TSMC generic process varactor model	neoflash	3	5726	Aug 4^th, 2006, 9:36am By: loose-electron
ESD I/O pads?	gsuarez	2	6513	Aug 2^nd, 2006, 9:46am By: loose-electron
IO design - where to start	gmork_0	2	4238	Aug 2^nd, 2006, 9:23am By: loose-electron
CMOS I/O series termination load line	Croaker	11	2708	Jun 13^th, 2006, 6:08am By: Croaker
puzzle about 5V tolerance of 3.3V CMOS	boris	2	4195	May 17^th, 2006, 1:58am By: mikki33
the DC coupling between the CML-PECL	dandelion	1	2929	May 15^th, 2006, 10:44pm By: ywguo

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