Designer’s Guide Community

Pages: 1 ... 4 5 6 7 8 ... 48

Subject	Started by	Replies	Views	Last post
embedded cores boot loaders	vicm6799	1	2565	Nov 18^th, 2015, 6:14pm By: loose-electron
phase of the gated ring oscillator	saralandry	3	3995	Nov 12^th, 2015, 7:26pm By: wandola
Phase Filter	AZADBAKHT	0	1741	Oct 9^th, 2015, 1:20am By: AZADBAKHT
Moved: mixed system simulation in cadence - Started by: jovial This Topic has been moved to AMS Simulators by Ken Kundert
Capacitor mismatch in sampler/DAC	DesertFox	1	2514	Sep 29^th, 2015, 9:52pm By: loose-electron
Moved: SNR calculation for VCO based ADC - Started by: Clark This Topic has been moved to Circuit Simulators by Ken Kundert
Phase Noise Adder for Cable	MarkS	1	2735	Sep 10^th, 2015, 10:34am By: loose-electron
Sigma-Delta Decimation Filter: CIC	Christoforos	1	4165	Aug 29^th, 2015, 6:04pm By: Burt Harris
Using an attenuator after the BPF attached to the sinewave gen. in ADC Testing	DesertFox	6	6852	Aug 4^th, 2015, 7:04am By: aaron_do
Verilog HDL simulation with ams simulator	medya	1	2806	Jul 13^th, 2015, 12:58pm By: Ken Kundert
Moved: How to create high impedance state in ams - Started by: nagamlan This Topic has been moved to Verilog-AMS by Ken Kundert
Digital modulation, ADC design, and RF section design questions	DavidX	2	1376	Jun 22^nd, 2015, 3:11pm By: DavidX
Moved: how to write data of the bus in a text file using veriloga - Started by: jovial This Topic has been moved to Verilog-AMS by Ken Kundert
Moved: Verilog-AMS Error in Virtuoso - Started by: Dshoter This Topic has been moved to Circuit Simulators by Ken Kundert
Optimal switch for Vdd/2 in a switched cap configuration	eternity	2	3306	Apr 2^nd, 2015, 12:57pm By: eternity
Moved: Decimation Filter in Verilog - can I use Blocking assignment - Started by: jdp This Topic has been moved to Verilog-AMS by Ken Kundert
How to calculate a resolution of a delta-sigma ADC?	CHL	2	3689	Mar 16^th, 2015, 9:09pm By: CHL
Moved: PLL specre simulator settings cause deadzone? - Started by: Jeffrey987 This Topic has been moved to Circuit Simulators by Ken Kundert
Sampling jittery signal with jittery clock	Kash	3	4439	Mar 11^th, 2015, 1:00pm By: Jeffrey987
PFD dead-zone	LowJitter	12	21132	Feb 27^th, 2015, 10:53am By: weber8722

Pages: 1 ... 4 5 6 7 8 ... 48

Normal Topic

Sticky Topic

Locked Topic

Sticky Locked Topic

Moved Topic

Global Announcement

Hot Topic (More than 10 Replies)

Very Hot Topic (More than 25 Replies)

You can view Topics in this Board.

You cannot post replies to Topics in this Board.
You cannot start new Topics in this Board.
You cannot start Polls in this Board.