Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Parametrized busses in Verilog-A	radius2	3	1611	Oct 8^th, 2012, 1:15am By: Frank Wiedmann
Charge pump modeling in Verilog-A	schwartz	0	7746	Sep 6^th, 2012, 12:37am By: schwartz
Simulation & Modeling of non linear magnetics	jerome_ams	7	12614	Aug 13^th, 2012, 5:46am By: Geoffrey_Coram
Verilog-A Statistical Variations	analog_power	13	14882	Aug 7^th, 2012, 4:07pm By: Hadi
real number model with Systemverilog	rampat	0	563	Jul 25^th, 2012, 9:36pm By: rampat
verilog to verilog-a conversion	cristiano.azzolini	2	5763	Jun 17^th, 2012, 1:47am By: cristiano.azzolini
verilog-A opamp output limiting	seanpai	4	17544	Apr 27^th, 2012, 5:46am By: Geoffrey_Coram
Variable phase shift model	dfot	3	4890	Mar 28^th, 2012, 11:22am By: boe
How to do random simulation on parameters defined in a verilog-A model?	manodipan	3	4681	Mar 9^th, 2012, 6:48am By: Geoffrey_Coram
Ideal model of 0/90 degrees phase splitter	Helge Stenstr�m	6	318	Mar 6^th, 2012, 4:22am By: weber8722
asking about the implicit equation when using verilog-A	dabier	3	181	Feb 23^rd, 2012, 3:36am By: boe
CMOS Image Sensor modeling	Nimrod Ben-Ari	1	3081	Feb 14^th, 2012, 1:34pm By: AndyBetts
how to create an n-stage RC filter in Verilog-A	sorgin1	3	7534	Feb 3^rd, 2012, 6:28am By: boe
problem with output stage model	danmc	5	1274	Jan 25^th, 2012, 8:53am By: Forum Administrator
Behavioral model for DCO	pumba007	0	2195	Jan 21^st, 2012, 11:03am By: pumba007
Verilog bus annotation using another bus	Ohn	0	1884	Jan 11^th, 2012, 7:12am By: Ohn
PRBS pattern length	raja.cedt	0	2444	Jan 5^th, 2012, 7:54am By: raja.cedt
try to simulate Ken Kundert's PLL phase noise prediction verilogA model	hearterinvest	0	3158	Jan 1^st, 2012, 8:08pm By: hearterinvest
Req example of pulldown command in VerilogA	animotion	6	7831	Dec 6^th, 2011, 10:57am By: boe
Moved: DRAM DESIGN - Started by: chandu28 This Topic has been moved to Mixed-Signal Design by Forum Administrator

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